Kconfig 6.5 KB

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  1. #
  2. # I2C subsystem configuration
  3. #
  4. menu "I2C support"
  5. config DM_I2C
  6. bool "Enable Driver Model for I2C drivers"
  7. depends on DM
  8. help
  9. Enable driver model for I2C. The I2C uclass interface: probe, read,
  10. write and speed, is implemented with the bus drivers operations,
  11. which provide methods for bus setting and data transfer. Each chip
  12. device (bus child) info is kept as parent platdata. The interface
  13. is defined in include/i2c.h. When i2c bus driver supports the i2c
  14. uclass, but the device drivers not, then DM_I2C_COMPAT config can
  15. be used as compatibility layer.
  16. config DM_I2C_COMPAT
  17. bool "Enable I2C compatibility layer"
  18. depends on DM
  19. help
  20. Enable old-style I2C functions for compatibility with existing code.
  21. This option can be enabled as a temporary measure to avoid needing
  22. to convert all code for a board in a single commit. It should not
  23. be enabled for any board in an official release.
  24. config I2C_CROS_EC_TUNNEL
  25. tristate "Chrome OS EC tunnel I2C bus"
  26. depends on CROS_EC
  27. help
  28. This provides an I2C bus that will tunnel i2c commands through to
  29. the other side of the Chrome OS EC to the I2C bus connected there.
  30. This will work whatever the interface used to talk to the EC (SPI,
  31. I2C or LPC). Some Chromebooks use this when the hardware design
  32. does not allow direct access to the main PMIC from the AP.
  33. config I2C_CROS_EC_LDO
  34. bool "Provide access to LDOs on the Chrome OS EC"
  35. depends on CROS_EC
  36. ---help---
  37. On many Chromebooks the main PMIC is inaccessible to the AP. This is
  38. often dealt with by using an I2C pass-through interface provided by
  39. the EC. On some unfortunate models (e.g. Spring) the pass-through
  40. is not available, and an LDO message is available instead. This
  41. option enables a driver which provides very basic access to those
  42. regulators, via the EC. We implement this as an I2C bus which
  43. emulates just the TPS65090 messages we know about. This is done to
  44. avoid duplicating the logic in the TPS65090 regulator driver for
  45. enabling/disabling an LDO.
  46. config DM_I2C_GPIO
  47. bool "Enable Driver Model for software emulated I2C bus driver"
  48. depends on DM_I2C && DM_GPIO
  49. help
  50. Enable the i2c bus driver emulation by using the GPIOs. The bus GPIO
  51. configuration is given by the device tree. Kernel-style device tree
  52. bindings are supported.
  53. Binding info: doc/device-tree-bindings/i2c/i2c-gpio.txt
  54. config SYS_I2C_AT91
  55. bool "Atmel I2C driver"
  56. depends on DM_I2C && ARCH_AT91
  57. help
  58. Add support for the Atmel I2C driver. A serious problem is that there
  59. is no documented way to issue repeated START conditions for more than
  60. two messages, as needed to support combined I2C messages. Use the
  61. i2c-gpio driver unless your system can cope with this limitation.
  62. Binding info: doc/device-tree-bindings/i2c/i2c-at91.txt
  63. config SYS_I2C_FSL
  64. bool "Freescale I2C bus driver"
  65. depends on DM_I2C
  66. help
  67. Add support for Freescale I2C busses as used on MPC8240, MPC8245, and
  68. MPC85xx processors.
  69. config SYS_I2C_CADENCE
  70. tristate "Cadence I2C Controller"
  71. depends on DM_I2C && (ARCH_ZYNQ || ARM64)
  72. help
  73. Say yes here to select Cadence I2C Host Controller. This controller is
  74. e.g. used by Xilinx Zynq.
  75. config SYS_I2C_DW
  76. bool "Designware I2C Controller"
  77. default n
  78. help
  79. Say yes here to select the Designware I2C Host Controller. This
  80. controller is used in various SoCs, e.g. the ST SPEAr, Altera
  81. SoCFPGA, Synopsys ARC700 and some Intel x86 SoCs.
  82. config SYS_I2C_DW_ENABLE_STATUS_UNSUPPORTED
  83. bool "DW I2C Enable Status Register not supported"
  84. depends on SYS_I2C_DW && (TARGET_SPEAR300 || TARGET_SPEAR310 || \
  85. TARGET_SPEAR320 || TARGET_SPEAR600 || TARGET_X600)
  86. default y
  87. help
  88. Some versions of the Designware I2C controller do not support the
  89. enable status register. This config option can be enabled in such
  90. cases.
  91. config SYS_I2C_INTEL
  92. bool "Intel I2C/SMBUS driver"
  93. depends on DM_I2C
  94. help
  95. Add support for the Intel SMBUS driver. So far this driver is just
  96. a stub which perhaps some basic init. There is no implementation of
  97. the I2C API meaning that any I2C operations will immediately fail
  98. for now.
  99. config SYS_I2C_MXC
  100. bool "NXP i.MX I2C driver"
  101. depends on MX6
  102. help
  103. Add support for the NXP i.MX I2C driver. This supports upto for bus
  104. channels and operating on standard mode upto 100 kbits/s and fast
  105. mode upto 400 kbits/s.
  106. config SYS_I2C_ROCKCHIP
  107. bool "Rockchip I2C driver"
  108. depends on DM_I2C
  109. help
  110. Add support for the Rockchip I2C driver. This is used with various
  111. Rockchip parts such as RK3126, RK3128, RK3036 and RK3288. All chips
  112. have several I2C ports and all are provided, controled by the
  113. device tree.
  114. config SYS_I2C_SANDBOX
  115. bool "Sandbox I2C driver"
  116. depends on SANDBOX && DM_I2C
  117. help
  118. Enable I2C support for sandbox. This is an emulation of a real I2C
  119. bus. Devices can be attached to the bus using the device tree
  120. which specifies the driver to use. As an example, see this device
  121. tree fragment from sandbox.dts. It shows that the I2C bus has a
  122. single EEPROM at address 0x2c (7-bit address) which is emulated by
  123. the driver for "sandbox,i2c-eeprom", which is in
  124. drivers/misc/i2c_eeprom_emul.c.
  125. i2c@0 {
  126. #address-cells = <1>;
  127. #size-cells = <0>;
  128. reg = <0>;
  129. compatible = "sandbox,i2c";
  130. clock-frequency = <400000>;
  131. eeprom@2c {
  132. reg = <0x2c>;
  133. compatible = "i2c-eeprom";
  134. emul {
  135. compatible = "sandbox,i2c-eeprom";
  136. sandbox,filename = "i2c.bin";
  137. sandbox,size = <128>;
  138. };
  139. };
  140. };
  141. config SYS_I2C_UNIPHIER
  142. bool "UniPhier I2C driver"
  143. depends on ARCH_UNIPHIER && DM_I2C
  144. default y
  145. help
  146. Support for UniPhier I2C controller driver. This I2C controller
  147. is used on PH1-LD4, PH1-sLD8 or older UniPhier SoCs.
  148. config SYS_I2C_UNIPHIER_F
  149. bool "UniPhier FIFO-builtin I2C driver"
  150. depends on ARCH_UNIPHIER && DM_I2C
  151. default y
  152. help
  153. Support for UniPhier FIFO-builtin I2C controller driver.
  154. This I2C controller is used on PH1-Pro4 or newer UniPhier SoCs.
  155. config SYS_I2C_MVTWSI
  156. bool "Marvell I2C driver"
  157. depends on DM_I2C
  158. help
  159. Support for Marvell I2C controllers as used on the orion5x and
  160. kirkwood SoC families.
  161. config TEGRA186_BPMP_I2C
  162. bool "Enable Tegra186 BPMP-based I2C driver"
  163. depends on TEGRA186_BPMP
  164. help
  165. Support for Tegra I2C controllers managed by the BPMP (Boot and
  166. Power Management Processor). On Tegra186, some I2C controllers are
  167. directly controlled by the main CPU, whereas others are controlled
  168. by the BPMP, and can only be accessed by the main CPU via IPC
  169. requests to the BPMP. This driver covers the latter case.
  170. source "drivers/i2c/muxes/Kconfig"
  171. endmenu