pcf8575_gpio.c 4.5 KB

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  1. /*
  2. * PCF8575 I2C GPIO EXPANDER DRIVER
  3. *
  4. * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
  5. *
  6. * Vignesh R <vigneshr@ti.com>
  7. *
  8. * SPDX-License-Identifier: GPL-2.0
  9. *
  10. *
  11. * Driver for TI PCF-8575 16-bit I2C gpio expander. Based on
  12. * gpio-pcf857x Linux Kernel(v4.7) driver.
  13. *
  14. * Copyright (C) 2007 David Brownell
  15. *
  16. */
  17. /*
  18. * NOTE: The driver and devicetree bindings are borrowed from Linux
  19. * Kernel, but driver does not support all PCF857x devices. It currently
  20. * supports PCF8575 16-bit expander by TI and NXP.
  21. *
  22. * TODO(vigneshr@ti.com):
  23. * Support 8 bit PCF857x compatible expanders.
  24. */
  25. #include <common.h>
  26. #include <dm.h>
  27. #include <i2c.h>
  28. #include <asm-generic/gpio.h>
  29. DECLARE_GLOBAL_DATA_PTR;
  30. struct pcf8575_chip {
  31. int gpio_count; /* No. GPIOs supported by the chip */
  32. /* NOTE: these chips have strange "quasi-bidirectional" I/O pins.
  33. * We can't actually know whether a pin is configured (a) as output
  34. * and driving the signal low, or (b) as input and reporting a low
  35. * value ... without knowing the last value written since the chip
  36. * came out of reset (if any). We can't read the latched output.
  37. * In short, the only reliable solution for setting up pin direction
  38. * is to do it explicitly.
  39. *
  40. * Using "out" avoids that trouble. When left initialized to zero,
  41. * our software copy of the "latch" then matches the chip's all-ones
  42. * reset state. Otherwise it flags pins to be driven low.
  43. */
  44. unsigned int out; /* software latch */
  45. const char *bank_name; /* Name of the expander bank */
  46. };
  47. /* Read/Write to 16-bit I/O expander */
  48. static int pcf8575_i2c_write_le16(struct udevice *dev, unsigned int word)
  49. {
  50. struct dm_i2c_chip *chip = dev_get_parent_platdata(dev);
  51. u8 buf[2] = { word & 0xff, word >> 8, };
  52. int ret;
  53. ret = dm_i2c_write(dev, 0, buf, 2);
  54. if (ret)
  55. printf("%s i2c write failed to addr %x\n", __func__,
  56. chip->chip_addr);
  57. return ret;
  58. }
  59. static int pcf8575_i2c_read_le16(struct udevice *dev)
  60. {
  61. struct dm_i2c_chip *chip = dev_get_parent_platdata(dev);
  62. u8 buf[2];
  63. int ret;
  64. ret = dm_i2c_read(dev, 0, buf, 2);
  65. if (ret) {
  66. printf("%s i2c read failed from addr %x\n", __func__,
  67. chip->chip_addr);
  68. return ret;
  69. }
  70. return (buf[1] << 8) | buf[0];
  71. }
  72. static int pcf8575_direction_input(struct udevice *dev, unsigned offset)
  73. {
  74. struct pcf8575_chip *plat = dev_get_platdata(dev);
  75. int status;
  76. plat->out |= BIT(offset);
  77. status = pcf8575_i2c_write_le16(dev, plat->out);
  78. return status;
  79. }
  80. static int pcf8575_direction_output(struct udevice *dev,
  81. unsigned int offset, int value)
  82. {
  83. struct pcf8575_chip *plat = dev_get_platdata(dev);
  84. int ret;
  85. if (value)
  86. plat->out |= BIT(offset);
  87. else
  88. plat->out &= ~BIT(offset);
  89. ret = pcf8575_i2c_write_le16(dev, plat->out);
  90. return ret;
  91. }
  92. static int pcf8575_get_value(struct udevice *dev, unsigned int offset)
  93. {
  94. int value;
  95. value = pcf8575_i2c_read_le16(dev);
  96. return (value < 0) ? value : ((value & BIT(offset)) >> offset);
  97. }
  98. static int pcf8575_set_value(struct udevice *dev, unsigned int offset,
  99. int value)
  100. {
  101. return pcf8575_direction_output(dev, offset, value);
  102. }
  103. static int pcf8575_ofdata_platdata(struct udevice *dev)
  104. {
  105. struct pcf8575_chip *plat = dev_get_platdata(dev);
  106. struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
  107. int n_latch;
  108. uc_priv->gpio_count = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
  109. "gpio-count", 16);
  110. uc_priv->bank_name = fdt_getprop(gd->fdt_blob, dev->of_offset,
  111. "gpio-bank-name", NULL);
  112. if (!uc_priv->bank_name)
  113. uc_priv->bank_name = fdt_get_name(gd->fdt_blob,
  114. dev->of_offset, NULL);
  115. n_latch = fdtdec_get_uint(gd->fdt_blob, dev->of_offset,
  116. "lines-initial-states", 0);
  117. plat->out = ~n_latch;
  118. return 0;
  119. }
  120. static int pcf8575_gpio_probe(struct udevice *dev)
  121. {
  122. struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
  123. debug("%s GPIO controller with %d gpios probed\n",
  124. uc_priv->bank_name, uc_priv->gpio_count);
  125. return 0;
  126. }
  127. static const struct dm_gpio_ops pcf8575_gpio_ops = {
  128. .direction_input = pcf8575_direction_input,
  129. .direction_output = pcf8575_direction_output,
  130. .get_value = pcf8575_get_value,
  131. .set_value = pcf8575_set_value,
  132. };
  133. static const struct udevice_id pcf8575_gpio_ids[] = {
  134. { .compatible = "nxp,pcf8575" },
  135. { .compatible = "ti,pcf8575" },
  136. { }
  137. };
  138. U_BOOT_DRIVER(gpio_pcf8575) = {
  139. .name = "gpio_pcf8575",
  140. .id = UCLASS_GPIO,
  141. .ops = &pcf8575_gpio_ops,
  142. .of_match = pcf8575_gpio_ids,
  143. .ofdata_to_platdata = pcf8575_ofdata_platdata,
  144. .probe = pcf8575_gpio_probe,
  145. .platdata_auto_alloc_size = sizeof(struct pcf8575_chip),
  146. };