mxc_gpio.c 8.1 KB

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  1. /*
  2. * Copyright (C) 2009
  3. * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
  4. *
  5. * Copyright (C) 2011
  6. * Stefano Babic, DENX Software Engineering, <sbabic@denx.de>
  7. *
  8. * SPDX-License-Identifier: GPL-2.0+
  9. */
  10. #include <common.h>
  11. #include <errno.h>
  12. #include <dm.h>
  13. #include <malloc.h>
  14. #include <asm/arch/imx-regs.h>
  15. #include <asm/gpio.h>
  16. #include <asm/io.h>
  17. enum mxc_gpio_direction {
  18. MXC_GPIO_DIRECTION_IN,
  19. MXC_GPIO_DIRECTION_OUT,
  20. };
  21. #define GPIO_PER_BANK 32
  22. struct mxc_gpio_plat {
  23. int bank_index;
  24. struct gpio_regs *regs;
  25. };
  26. struct mxc_bank_info {
  27. struct gpio_regs *regs;
  28. };
  29. #ifndef CONFIG_DM_GPIO
  30. #define GPIO_TO_PORT(n) (n / 32)
  31. /* GPIO port description */
  32. static unsigned long gpio_ports[] = {
  33. [0] = GPIO1_BASE_ADDR,
  34. [1] = GPIO2_BASE_ADDR,
  35. [2] = GPIO3_BASE_ADDR,
  36. #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
  37. defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
  38. defined(CONFIG_MX7)
  39. [3] = GPIO4_BASE_ADDR,
  40. #endif
  41. #if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
  42. defined(CONFIG_MX7)
  43. [4] = GPIO5_BASE_ADDR,
  44. #ifndef CONFIG_MX6UL
  45. [5] = GPIO6_BASE_ADDR,
  46. #endif
  47. #endif
  48. #if defined(CONFIG_MX53) || defined(CONFIG_MX6) || defined(CONFIG_MX7)
  49. #ifndef CONFIG_MX6UL
  50. [6] = GPIO7_BASE_ADDR,
  51. #endif
  52. #endif
  53. };
  54. static int mxc_gpio_direction(unsigned int gpio,
  55. enum mxc_gpio_direction direction)
  56. {
  57. unsigned int port = GPIO_TO_PORT(gpio);
  58. struct gpio_regs *regs;
  59. u32 l;
  60. if (port >= ARRAY_SIZE(gpio_ports))
  61. return -1;
  62. gpio &= 0x1f;
  63. regs = (struct gpio_regs *)gpio_ports[port];
  64. l = readl(&regs->gpio_dir);
  65. switch (direction) {
  66. case MXC_GPIO_DIRECTION_OUT:
  67. l |= 1 << gpio;
  68. break;
  69. case MXC_GPIO_DIRECTION_IN:
  70. l &= ~(1 << gpio);
  71. }
  72. writel(l, &regs->gpio_dir);
  73. return 0;
  74. }
  75. int gpio_set_value(unsigned gpio, int value)
  76. {
  77. unsigned int port = GPIO_TO_PORT(gpio);
  78. struct gpio_regs *regs;
  79. u32 l;
  80. if (port >= ARRAY_SIZE(gpio_ports))
  81. return -1;
  82. gpio &= 0x1f;
  83. regs = (struct gpio_regs *)gpio_ports[port];
  84. l = readl(&regs->gpio_dr);
  85. if (value)
  86. l |= 1 << gpio;
  87. else
  88. l &= ~(1 << gpio);
  89. writel(l, &regs->gpio_dr);
  90. return 0;
  91. }
  92. int gpio_get_value(unsigned gpio)
  93. {
  94. unsigned int port = GPIO_TO_PORT(gpio);
  95. struct gpio_regs *regs;
  96. u32 val;
  97. if (port >= ARRAY_SIZE(gpio_ports))
  98. return -1;
  99. gpio &= 0x1f;
  100. regs = (struct gpio_regs *)gpio_ports[port];
  101. val = (readl(&regs->gpio_psr) >> gpio) & 0x01;
  102. return val;
  103. }
  104. int gpio_request(unsigned gpio, const char *label)
  105. {
  106. unsigned int port = GPIO_TO_PORT(gpio);
  107. if (port >= ARRAY_SIZE(gpio_ports))
  108. return -1;
  109. return 0;
  110. }
  111. int gpio_free(unsigned gpio)
  112. {
  113. return 0;
  114. }
  115. int gpio_direction_input(unsigned gpio)
  116. {
  117. return mxc_gpio_direction(gpio, MXC_GPIO_DIRECTION_IN);
  118. }
  119. int gpio_direction_output(unsigned gpio, int value)
  120. {
  121. int ret = gpio_set_value(gpio, value);
  122. if (ret < 0)
  123. return ret;
  124. return mxc_gpio_direction(gpio, MXC_GPIO_DIRECTION_OUT);
  125. }
  126. #endif
  127. #ifdef CONFIG_DM_GPIO
  128. #include <fdtdec.h>
  129. DECLARE_GLOBAL_DATA_PTR;
  130. static int mxc_gpio_is_output(struct gpio_regs *regs, int offset)
  131. {
  132. u32 val;
  133. val = readl(&regs->gpio_dir);
  134. return val & (1 << offset) ? 1 : 0;
  135. }
  136. static void mxc_gpio_bank_direction(struct gpio_regs *regs, int offset,
  137. enum mxc_gpio_direction direction)
  138. {
  139. u32 l;
  140. l = readl(&regs->gpio_dir);
  141. switch (direction) {
  142. case MXC_GPIO_DIRECTION_OUT:
  143. l |= 1 << offset;
  144. break;
  145. case MXC_GPIO_DIRECTION_IN:
  146. l &= ~(1 << offset);
  147. }
  148. writel(l, &regs->gpio_dir);
  149. }
  150. static void mxc_gpio_bank_set_value(struct gpio_regs *regs, int offset,
  151. int value)
  152. {
  153. u32 l;
  154. l = readl(&regs->gpio_dr);
  155. if (value)
  156. l |= 1 << offset;
  157. else
  158. l &= ~(1 << offset);
  159. writel(l, &regs->gpio_dr);
  160. }
  161. static int mxc_gpio_bank_get_value(struct gpio_regs *regs, int offset)
  162. {
  163. return (readl(&regs->gpio_psr) >> offset) & 0x01;
  164. }
  165. /* set GPIO pin 'gpio' as an input */
  166. static int mxc_gpio_direction_input(struct udevice *dev, unsigned offset)
  167. {
  168. struct mxc_bank_info *bank = dev_get_priv(dev);
  169. /* Configure GPIO direction as input. */
  170. mxc_gpio_bank_direction(bank->regs, offset, MXC_GPIO_DIRECTION_IN);
  171. return 0;
  172. }
  173. /* set GPIO pin 'gpio' as an output, with polarity 'value' */
  174. static int mxc_gpio_direction_output(struct udevice *dev, unsigned offset,
  175. int value)
  176. {
  177. struct mxc_bank_info *bank = dev_get_priv(dev);
  178. /* Configure GPIO output value. */
  179. mxc_gpio_bank_set_value(bank->regs, offset, value);
  180. /* Configure GPIO direction as output. */
  181. mxc_gpio_bank_direction(bank->regs, offset, MXC_GPIO_DIRECTION_OUT);
  182. return 0;
  183. }
  184. /* read GPIO IN value of pin 'gpio' */
  185. static int mxc_gpio_get_value(struct udevice *dev, unsigned offset)
  186. {
  187. struct mxc_bank_info *bank = dev_get_priv(dev);
  188. return mxc_gpio_bank_get_value(bank->regs, offset);
  189. }
  190. /* write GPIO OUT value to pin 'gpio' */
  191. static int mxc_gpio_set_value(struct udevice *dev, unsigned offset,
  192. int value)
  193. {
  194. struct mxc_bank_info *bank = dev_get_priv(dev);
  195. mxc_gpio_bank_set_value(bank->regs, offset, value);
  196. return 0;
  197. }
  198. static int mxc_gpio_get_function(struct udevice *dev, unsigned offset)
  199. {
  200. struct mxc_bank_info *bank = dev_get_priv(dev);
  201. /* GPIOF_FUNC is not implemented yet */
  202. if (mxc_gpio_is_output(bank->regs, offset))
  203. return GPIOF_OUTPUT;
  204. else
  205. return GPIOF_INPUT;
  206. }
  207. static const struct dm_gpio_ops gpio_mxc_ops = {
  208. .direction_input = mxc_gpio_direction_input,
  209. .direction_output = mxc_gpio_direction_output,
  210. .get_value = mxc_gpio_get_value,
  211. .set_value = mxc_gpio_set_value,
  212. .get_function = mxc_gpio_get_function,
  213. };
  214. static int mxc_gpio_probe(struct udevice *dev)
  215. {
  216. struct mxc_bank_info *bank = dev_get_priv(dev);
  217. struct mxc_gpio_plat *plat = dev_get_platdata(dev);
  218. struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
  219. int banknum;
  220. char name[18], *str;
  221. banknum = plat->bank_index;
  222. sprintf(name, "GPIO%d_", banknum + 1);
  223. str = strdup(name);
  224. if (!str)
  225. return -ENOMEM;
  226. uc_priv->bank_name = str;
  227. uc_priv->gpio_count = GPIO_PER_BANK;
  228. bank->regs = plat->regs;
  229. return 0;
  230. }
  231. static int mxc_gpio_bind(struct udevice *dev)
  232. {
  233. struct mxc_gpio_plat *plat = dev->platdata;
  234. fdt_addr_t addr;
  235. /*
  236. * If platdata already exsits, directly return.
  237. * Actually only when DT is not supported, platdata
  238. * is statically initialized in U_BOOT_DEVICES.Here
  239. * will return.
  240. */
  241. if (plat)
  242. return 0;
  243. addr = dev_get_addr(dev);
  244. if (addr == FDT_ADDR_T_NONE)
  245. return -ENODEV;
  246. /*
  247. * TODO:
  248. * When every board is converted to driver model and DT is supported,
  249. * this can be done by auto-alloc feature, but not using calloc
  250. * to alloc memory for platdata.
  251. */
  252. plat = calloc(1, sizeof(*plat));
  253. if (!plat)
  254. return -ENOMEM;
  255. plat->regs = (struct gpio_regs *)addr;
  256. plat->bank_index = dev->req_seq;
  257. dev->platdata = plat;
  258. return 0;
  259. }
  260. static const struct udevice_id mxc_gpio_ids[] = {
  261. { .compatible = "fsl,imx35-gpio" },
  262. { }
  263. };
  264. U_BOOT_DRIVER(gpio_mxc) = {
  265. .name = "gpio_mxc",
  266. .id = UCLASS_GPIO,
  267. .ops = &gpio_mxc_ops,
  268. .probe = mxc_gpio_probe,
  269. .priv_auto_alloc_size = sizeof(struct mxc_bank_info),
  270. .of_match = mxc_gpio_ids,
  271. .bind = mxc_gpio_bind,
  272. };
  273. #if !CONFIG_IS_ENABLED(OF_CONTROL)
  274. static const struct mxc_gpio_plat mxc_plat[] = {
  275. { 0, (struct gpio_regs *)GPIO1_BASE_ADDR },
  276. { 1, (struct gpio_regs *)GPIO2_BASE_ADDR },
  277. { 2, (struct gpio_regs *)GPIO3_BASE_ADDR },
  278. #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
  279. defined(CONFIG_MX53) || defined(CONFIG_MX6)
  280. { 3, (struct gpio_regs *)GPIO4_BASE_ADDR },
  281. #endif
  282. #if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6)
  283. { 4, (struct gpio_regs *)GPIO5_BASE_ADDR },
  284. { 5, (struct gpio_regs *)GPIO6_BASE_ADDR },
  285. #endif
  286. #if defined(CONFIG_MX53) || defined(CONFIG_MX6)
  287. { 6, (struct gpio_regs *)GPIO7_BASE_ADDR },
  288. #endif
  289. };
  290. U_BOOT_DEVICES(mxc_gpios) = {
  291. { "gpio_mxc", &mxc_plat[0] },
  292. { "gpio_mxc", &mxc_plat[1] },
  293. { "gpio_mxc", &mxc_plat[2] },
  294. #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
  295. defined(CONFIG_MX53) || defined(CONFIG_MX6)
  296. { "gpio_mxc", &mxc_plat[3] },
  297. #endif
  298. #if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6)
  299. { "gpio_mxc", &mxc_plat[4] },
  300. { "gpio_mxc", &mxc_plat[5] },
  301. #endif
  302. #if defined(CONFIG_MX53) || defined(CONFIG_MX6)
  303. { "gpio_mxc", &mxc_plat[6] },
  304. #endif
  305. };
  306. #endif
  307. #endif