stratixv.c 2.2 KB

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  1. /*
  2. * Copyright (C) 2016 Stefan Roese <sr@denx.de>
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. #include <common.h>
  7. #include <altera.h>
  8. #include <spi.h>
  9. #include <asm/io.h>
  10. #include <linux/errno.h>
  11. /* Write the RBF data to FPGA via SPI */
  12. static int program_write(int spi_bus, int spi_dev, const void *rbf_data,
  13. unsigned long rbf_size)
  14. {
  15. struct spi_slave *slave;
  16. int ret;
  17. debug("%s (%d): data=%p size=%ld\n",
  18. __func__, __LINE__, rbf_data, rbf_size);
  19. /* FIXME: How to get the max. SPI clock and SPI mode? */
  20. slave = spi_setup_slave(spi_bus, spi_dev, 27777777, SPI_MODE_3);
  21. if (!slave)
  22. return -1;
  23. if (spi_claim_bus(slave))
  24. return -1;
  25. ret = spi_xfer(slave, rbf_size * 8, rbf_data, (void *)rbf_data,
  26. SPI_XFER_BEGIN | SPI_XFER_END);
  27. spi_release_bus(slave);
  28. return ret;
  29. }
  30. /*
  31. * This is the interface used by FPGA driver.
  32. * Return 0 for sucess, non-zero for error.
  33. */
  34. int stratixv_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
  35. {
  36. altera_board_specific_func *pfns = desc->iface_fns;
  37. int cookie = desc->cookie;
  38. int spi_bus;
  39. int spi_dev;
  40. int ret = 0;
  41. if ((u32)rbf_data & 0x3) {
  42. puts("FPGA: Unaligned data, realign to 32bit boundary.\n");
  43. return -EINVAL;
  44. }
  45. /* Run the pre configuration function if there is one */
  46. if (pfns->pre)
  47. (pfns->pre)(cookie);
  48. /* Establish the initial state */
  49. if (pfns->config) {
  50. /* De-assert nCONFIG */
  51. (pfns->config)(false, true, cookie);
  52. /* nConfig minimum low pulse width is 2us */
  53. udelay(200);
  54. /* Assert nCONFIG */
  55. (pfns->config)(true, true, cookie);
  56. /* nCONFIG high to first rising clock on DCLK min 1506 us */
  57. udelay(1600);
  58. }
  59. /* Write the RBF data to FPGA */
  60. if (pfns->write) {
  61. /*
  62. * Use board specific data function to write bitstream
  63. * into the FPGA
  64. */
  65. ret = (pfns->write)(rbf_data, rbf_size, true, cookie);
  66. } else {
  67. /*
  68. * Use common SPI functions to write bitstream into the
  69. * FPGA
  70. */
  71. spi_bus = COOKIE2SPI_BUS(cookie);
  72. spi_dev = COOKIE2SPI_DEV(cookie);
  73. ret = program_write(spi_bus, spi_dev, rbf_data, rbf_size);
  74. }
  75. if (ret)
  76. return ret;
  77. /* Check done pin */
  78. if (pfns->done) {
  79. ret = (pfns->done)(cookie);
  80. if (ret)
  81. printf("Error: DONE not set (ret=%d)!\n", ret);
  82. }
  83. return ret;
  84. }