Test/board-support/u-boot-2017.01+gitAUTOINC+340fb36f04-g340fb36f04/drivers/clk/exynos/clk-pll.h

/*
 * Exynos PLL helper functions for clock drivers.
 * Copyright (C) 2016 Samsung Electronics
 * Thomas Abraham <thomas.ab@samsung.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

unsigned long pll145x_get_rate(unsigned int *con1, unsigned long fin_freq);