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ts4600
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iomux.c

iomux.c 4.8 KB
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  1. /*
    2. 

  2.  * (C) Copyright 2016 Savoir-faire Linux Inc.
    3. 

  3.  *
    4. 

  4.  * Author: Sebastien Bourdelin <sebastien.bourdelin@savoirfairelinux.com>
    5. 

  5.  *
    6. 

  6.  * Based on work from TS7680 code by:
    7. 

  7.  *   Kris Bahnsen <kris@embeddedarm.com>
    8. 

  8.  *   Mark Featherston <mark@embeddedarm.com>
    9. 

  9.  *   https://github.com/embeddedarm/u-boot/tree/master/board/technologic/ts7680
    10. 

  10.  *
    11. 

  11.  * Derived from MX28EVK code by
    12. 

  12.  *   Freescale Semiconductor, Inc.
    13. 

  13.  *
    14. 

  14.  * SPDX-License-Identifier:	GPL-2.0+
    15. 

  15.  */
    16. 

  16. 

  17. #include <common.h>
    18. 

  18. #include <config.h>
    19. 

  19. #include <asm/io.h>
    20. 

  20. #include <asm/arch/iomux-mx28.h>
    21. 

  21. #include <asm/arch/imx-regs.h>
    22. 

  22. #include <asm/arch/sys_proto.h>
    23. 

  23. 

  24. #define	MUX_CONFIG_SSP0	(MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
    25. 

  25. #define	MUX_CONFIG_EMI	(MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL)
    26. 

  26. 

  27. const iomux_cfg_t iomux_setup[] = {
    28. 

  28. 	/* DUART */
    29. 

  29. 	MX28_PAD_PWM0__DUART_RX,
    30. 

  30. 	MX28_PAD_PWM1__DUART_TX,
    31. 

  31. 

  32. 	/* MMC0 */
    33. 

  33. 	MX28_PAD_SSP0_DATA0__SSP0_D0 | MUX_CONFIG_SSP0,
    34. 

  34. 	MX28_PAD_SSP0_DATA1__SSP0_D1 | MUX_CONFIG_SSP0,
    35. 

  35. 	MX28_PAD_SSP0_DATA2__SSP0_D2 | MUX_CONFIG_SSP0,
    36. 

  36. 	MX28_PAD_SSP0_DATA3__SSP0_D3 | MUX_CONFIG_SSP0,
    37. 

  37. 	MX28_PAD_SSP0_CMD__SSP0_CMD | MUX_CONFIG_SSP0,
    38. 

  38. 	MX28_PAD_SSP0_SCK__SSP0_SCK |
    39. 

  39. 		(MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
    40. 

  40. 

  41. 	/* MMC0 slot power enable */
    42. 

  42. 	MX28_PAD_PWM3__GPIO_3_28 |
    43. 

  43. 		(MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
    44. 

  44. 

  45. 	/* EMI */
    46. 

  46. 	MX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI,
    47. 

  47. 	MX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI,
    48. 

  48. 	MX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI,
    49. 

  49. 	MX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI,
    50. 

  50. 	MX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI,
    51. 

  51. 	MX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI,
    52. 

  52. 	MX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI,
    53. 

  53. 	MX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI,
    54. 

  54. 	MX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI,
    55. 

  55. 	MX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI,
    56. 

  56. 	MX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI,
    57. 

  57. 	MX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI,
    58. 

  58. 	MX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI,
    59. 

  59. 	MX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI,
    60. 

  60. 	MX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI,
    61. 

  61. 	MX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI,
    62. 

  62. 	MX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI,
    63. 

  63. 	MX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI,
    64. 

  64. 	MX28_PAD_EMI_ODT1__EMI_ODT1 | MUX_CONFIG_EMI,
    65. 

  65. 	MX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI,
    66. 

  66. 	MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | MUX_CONFIG_EMI,
    67. 

  67. 	MX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI,
    68. 

  68. 	MX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI,
    69. 

  69. 	MX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI,
    70. 

  70. 	MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI,
    71. 

  71. 	MX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI,
    72. 

  72. 	MX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI,
    73. 

  73. 	MX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI,
    74. 

  74. 	MX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI,
    75. 

  75. 	MX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI,
    76. 

  76. 	MX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI,
    77. 

  77. 	MX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI,
    78. 

  78. 	MX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI,
    79. 

  79. 	MX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI,
    80. 

  80. 	MX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI,
    81. 

  81. 	MX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI,
    82. 

  82. 	MX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI,
    83. 

  83. 	MX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI,
    84. 

  84. 	MX28_PAD_EMI_A13__EMI_ADDR13 | MUX_CONFIG_EMI,
    85. 

  85. 	MX28_PAD_EMI_A14__EMI_ADDR14 | MUX_CONFIG_EMI,
    86. 

  86. 	MX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI,
    87. 

  87. 	MX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI,
    88. 

  88. 	MX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI,
    89. 

  89. 	MX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI,
    90. 

  90. 	MX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI,
    91. 

  91. 	MX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI,
    92. 

  92. 	MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI,
    93. 

  93. 	MX28_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI,
    94. 

  94. 	MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI,
    95. 

  95. 

  96. 	/* I2C */
    97. 

  97. 	MX28_PAD_I2C0_SCL__I2C0_SCL,
    98. 

  98. 	MX28_PAD_I2C0_SDA__I2C0_SDA,
    99. 

  99. 

  100. };
    101. 

  101. 

  102. #define HW_DRAM_CTL29	(0x74 >> 2)
    103. 

  103. #define CS_MAP		0xf
    104. 

  104. #define COLUMN_SIZE	0x2
    105. 

  105. #define ADDR_PINS	0x1
    106. 

  106. #define APREBIT		0xa
    107. 

  107. 

  108. #define HW_DRAM_CTL29_CONFIG	(CS_MAP << 24 | COLUMN_SIZE << 16 | \
    109. 

  109. 					ADDR_PINS << 8 | APREBIT)
    110. 

  110. 

  111. #define HW_DRAM_CTL39	(0x9c >> 2)
    112. 

  112. #define TFAW		0xb
    113. 

  113. #define TDLL		0xc8
    114. 

  114. 

  115. #define HW_DRAM_CTL39_CONFIG	(TFAW << 24 | TDLL)
    116. 

  116. 

  117. #define HW_DRAM_CTL41	(0xa4 >> 2)
    118. 

  118. #define TPDEX		0x2
    119. 

  119. #define TRCD_INT	0x4
    120. 

  120. #define TRC		0xd
    121. 

  121. 

  122. #define HW_DRAM_CTL41_CONFIG	(TPDEX << 24 | TRCD_INT << 8 | TRC)
    123. 

  123. 

  124. #define HW_DRAM_CTL42	(0xa8 >> 2)
    125. 

  125. #define TRAS_MAX	0x36a6
    126. 

  126. #define TRAS_MIN	0xa
    127. 

  127. 

  128. #define HW_DRAM_CTL42_CONFIG  (TRAS_MAX << 8 | TRAS_MIN)
    129. 

  129. 

  130. #define HW_DRAM_CTL43	(0xac >> 2)
    131. 

  131. #define TRP		0x4
    132. 

  132. #define TRFC		0x27
    133. 

  133. #define TREF		0x2a0
    134. 

  134. 

  135. #define HW_DRAM_CTL43_CONFIG (TRP << 24 | TRFC << 16 | TREF)
    136. 

  136. 

  137. void mxs_adjust_memory_params(uint32_t *dram_vals)
    138. 

  138. {
    139. 

  139. 	dram_vals[HW_DRAM_CTL29] = HW_DRAM_CTL29_CONFIG;
    140. 

  140. 	dram_vals[HW_DRAM_CTL39] = HW_DRAM_CTL39_CONFIG;
    141. 

  141. 	dram_vals[HW_DRAM_CTL41] = HW_DRAM_CTL41_CONFIG;
    142. 

  142. 	dram_vals[HW_DRAM_CTL42] = HW_DRAM_CTL42_CONFIG;
    143. 

  143. 	dram_vals[HW_DRAM_CTL43] = HW_DRAM_CTL43_CONFIG;
    144. 

  144. }
    145. 

  145. 

  146. void board_init_ll(const uint32_t arg, const uint32_t *resptr)
    147. 

  147. {
    148. 

  148. 	mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup));
    149. 

  149. }
    150.