omapl138_lcdk.c 8.3 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373
  1. /*
  2. * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
  3. *
  4. * Based on da850evm.c. Original Copyrights follow:
  5. *
  6. * Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson@gefanuc.com>
  7. * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
  8. *
  9. * SPDX-License-Identifier: GPL-2.0+
  10. */
  11. #include <common.h>
  12. #include <i2c.h>
  13. #include <net.h>
  14. #include <netdev.h>
  15. #include <spi.h>
  16. #include <spi_flash.h>
  17. #include <asm/arch/hardware.h>
  18. #include <asm/ti-common/davinci_nand.h>
  19. #include <asm/io.h>
  20. #include <linux/errno.h>
  21. #include <asm/arch/davinci_misc.h>
  22. #ifdef CONFIG_DAVINCI_MMC
  23. #include <mmc.h>
  24. #include <asm/arch/sdmmc_defs.h>
  25. #endif
  26. DECLARE_GLOBAL_DATA_PTR;
  27. #define pinmux(x) (&davinci_syscfg_regs->pinmux[x])
  28. #ifdef CONFIG_DAVINCI_MMC
  29. /* MMC0 pin muxer settings */
  30. const struct pinmux_config mmc0_pins[] = {
  31. /* GP0[11] is required for SD to work on Rev 3 EVMs */
  32. { pinmux(0), 8, 4 }, /* GP0[11] */
  33. { pinmux(10), 2, 0 }, /* MMCSD0_CLK */
  34. { pinmux(10), 2, 1 }, /* MMCSD0_CMD */
  35. { pinmux(10), 2, 2 }, /* MMCSD0_DAT_0 */
  36. { pinmux(10), 2, 3 }, /* MMCSD0_DAT_1 */
  37. { pinmux(10), 2, 4 }, /* MMCSD0_DAT_2 */
  38. { pinmux(10), 2, 5 }, /* MMCSD0_DAT_3 */
  39. /* LCDK supports only 4-bit mode, remaining pins are not configured */
  40. };
  41. #endif
  42. /* UART pin muxer settings */
  43. static const struct pinmux_config uart_pins[] = {
  44. { pinmux(0), 4, 6 },
  45. { pinmux(0), 4, 7 },
  46. { pinmux(4), 2, 4 },
  47. { pinmux(4), 2, 5 }
  48. };
  49. #ifdef CONFIG_DRIVER_TI_EMAC
  50. static const struct pinmux_config emac_pins[] = {
  51. { pinmux(2), 8, 1 },
  52. { pinmux(2), 8, 2 },
  53. { pinmux(2), 8, 3 },
  54. { pinmux(2), 8, 4 },
  55. { pinmux(2), 8, 5 },
  56. { pinmux(2), 8, 6 },
  57. { pinmux(2), 8, 7 },
  58. { pinmux(3), 8, 0 },
  59. { pinmux(3), 8, 1 },
  60. { pinmux(3), 8, 2 },
  61. { pinmux(3), 8, 3 },
  62. { pinmux(3), 8, 4 },
  63. { pinmux(3), 8, 5 },
  64. { pinmux(3), 8, 6 },
  65. { pinmux(3), 8, 7 },
  66. { pinmux(4), 8, 0 },
  67. { pinmux(4), 8, 1 }
  68. };
  69. #endif /* CONFIG_DRIVER_TI_EMAC */
  70. /* I2C pin muxer settings */
  71. static const struct pinmux_config i2c_pins[] = {
  72. { pinmux(4), 2, 2 },
  73. { pinmux(4), 2, 3 }
  74. };
  75. #ifdef CONFIG_NAND_DAVINCI
  76. const struct pinmux_config nand_pins[] = {
  77. { pinmux(7), 1, 1 },
  78. { pinmux(7), 1, 2 },
  79. { pinmux(7), 1, 4 },
  80. { pinmux(7), 1, 5 },
  81. { pinmux(8), 1, 0 },
  82. { pinmux(8), 1, 1 },
  83. { pinmux(8), 1, 2 },
  84. { pinmux(8), 1, 3 },
  85. { pinmux(8), 1, 4 },
  86. { pinmux(8), 1, 5 },
  87. { pinmux(8), 1, 6 },
  88. { pinmux(8), 1, 7 },
  89. { pinmux(9), 1, 0 },
  90. { pinmux(9), 1, 1 },
  91. { pinmux(9), 1, 2 },
  92. { pinmux(9), 1, 3 },
  93. { pinmux(9), 1, 4 },
  94. { pinmux(9), 1, 5 },
  95. { pinmux(9), 1, 6 },
  96. { pinmux(9), 1, 7 },
  97. { pinmux(12), 1, 5 },
  98. { pinmux(12), 1, 6 }
  99. };
  100. #endif
  101. #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
  102. #define HAS_RMII 1
  103. #else
  104. #define HAS_RMII 0
  105. #endif
  106. const struct pinmux_resource pinmuxes[] = {
  107. PINMUX_ITEM(uart_pins),
  108. PINMUX_ITEM(i2c_pins),
  109. #ifdef CONFIG_NAND_DAVINCI
  110. PINMUX_ITEM(nand_pins),
  111. #endif
  112. };
  113. const int pinmuxes_size = ARRAY_SIZE(pinmuxes);
  114. const struct lpsc_resource lpsc[] = {
  115. { DAVINCI_LPSC_AEMIF }, /* NAND, NOR */
  116. { DAVINCI_LPSC_SPI1 }, /* Serial Flash */
  117. { DAVINCI_LPSC_EMAC }, /* image download */
  118. { DAVINCI_LPSC_UART2 }, /* console */
  119. { DAVINCI_LPSC_GPIO },
  120. #ifdef CONFIG_DAVINCI_MMC
  121. { DAVINCI_LPSC_MMC_SD },
  122. #endif
  123. };
  124. const int lpsc_size = ARRAY_SIZE(lpsc);
  125. #ifndef CONFIG_DA850_EVM_MAX_CPU_CLK
  126. #define CONFIG_DA850_EVM_MAX_CPU_CLK 456000000
  127. #endif
  128. /*
  129. * get_board_rev() - setup to pass kernel board revision information
  130. * Returns:
  131. * bit[0-3] Maximum cpu clock rate supported by onboard SoC
  132. * 0000b - 300 MHz
  133. * 0001b - 372 MHz
  134. * 0010b - 408 MHz
  135. * 0011b - 456 MHz
  136. */
  137. u32 get_board_rev(void)
  138. {
  139. return 0;
  140. }
  141. int board_early_init_f(void)
  142. {
  143. /*
  144. * Power on required peripherals
  145. * ARM does not have access by default to PSC0 and PSC1
  146. * assuming here that the DSP bootloader has set the IOPU
  147. * such that PSC access is available to ARM
  148. */
  149. if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc)))
  150. return 1;
  151. return 0;
  152. }
  153. int board_init(void)
  154. {
  155. #ifndef CONFIG_USE_IRQ
  156. irq_init();
  157. #endif
  158. /* arch number of the board */
  159. gd->bd->bi_arch_number = MACH_TYPE_OMAPL138_LCDK;
  160. /* address of boot parameters */
  161. gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
  162. /* setup the SUSPSRC for ARM to control emulation suspend */
  163. writel(readl(&davinci_syscfg_regs->suspsrc) &
  164. ~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C |
  165. DAVINCI_SYSCFG_SUSPSRC_SPI1 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 |
  166. DAVINCI_SYSCFG_SUSPSRC_UART2),
  167. &davinci_syscfg_regs->suspsrc);
  168. /* configure pinmux settings */
  169. if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes)))
  170. return 1;
  171. #ifdef CONFIG_NAND_DAVINCI
  172. /*
  173. * NAND CS setup - cycle counts based on da850evm NAND timings in the
  174. * Linux kernel @ 25MHz EMIFA
  175. */
  176. writel((DAVINCI_ABCR_WSETUP(15) |
  177. DAVINCI_ABCR_WSTROBE(63) |
  178. DAVINCI_ABCR_WHOLD(7) |
  179. DAVINCI_ABCR_RSETUP(15) |
  180. DAVINCI_ABCR_RSTROBE(63) |
  181. DAVINCI_ABCR_RHOLD(7) |
  182. DAVINCI_ABCR_TA(3) |
  183. DAVINCI_ABCR_ASIZE_16BIT),
  184. &davinci_emif_regs->ab2cr); /* CS3 */
  185. #endif
  186. #ifdef CONFIG_DAVINCI_MMC
  187. if (davinci_configure_pin_mux(mmc0_pins, ARRAY_SIZE(mmc0_pins)) != 0)
  188. return 1;
  189. #endif
  190. #ifdef CONFIG_DRIVER_TI_EMAC
  191. if (davinci_configure_pin_mux(emac_pins, ARRAY_SIZE(emac_pins)) != 0)
  192. return 1;
  193. davinci_emac_mii_mode_sel(HAS_RMII);
  194. #endif /* CONFIG_DRIVER_TI_EMAC */
  195. /* enable the console UART */
  196. writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
  197. DAVINCI_UART_PWREMU_MGMT_UTRST),
  198. &davinci_uart2_ctrl_regs->pwremu_mgmt);
  199. return 0;
  200. }
  201. #ifdef CONFIG_DRIVER_TI_EMAC
  202. /*
  203. * Initializes on-board ethernet controllers.
  204. */
  205. int board_eth_init(bd_t *bis)
  206. {
  207. if (!davinci_emac_initialize()) {
  208. printf("Error: Ethernet init failed!\n");
  209. return -1;
  210. }
  211. return 0;
  212. }
  213. #endif /* CONFIG_DRIVER_TI_EMAC */
  214. #define CFG_MAC_ADDR_SPI_BUS 0
  215. #define CFG_MAC_ADDR_SPI_CS 0
  216. #define CFG_MAC_ADDR_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
  217. #define CFG_MAC_ADDR_SPI_MODE SPI_MODE_3
  218. #define CFG_MAC_ADDR_OFFSET (flash->size - SZ_64K)
  219. static int get_mac_addr(u8 *addr)
  220. {
  221. /* Need to find a way to get MAC ADDRESS */
  222. return 0;
  223. }
  224. void dsp_lpsc_on(unsigned domain, unsigned int id)
  225. {
  226. dv_reg_p mdstat, mdctl, ptstat, ptcmd;
  227. struct davinci_psc_regs *psc_regs;
  228. psc_regs = davinci_psc0_regs;
  229. mdstat = &psc_regs->psc0.mdstat[id];
  230. mdctl = &psc_regs->psc0.mdctl[id];
  231. ptstat = &psc_regs->ptstat;
  232. ptcmd = &psc_regs->ptcmd;
  233. while (*ptstat & (0x1 << domain))
  234. ;
  235. if ((*mdstat & 0x1f) == 0x03)
  236. return; /* Already on and enabled */
  237. *mdctl |= 0x03;
  238. *ptcmd = 0x1 << domain;
  239. while (*ptstat & (0x1 << domain))
  240. ;
  241. while ((*mdstat & 0x1f) != 0x03)
  242. ; /* Probably an overkill... */
  243. }
  244. static void dspwake(void)
  245. {
  246. unsigned *resetvect = (unsigned *)DAVINCI_L3CBARAM_BASE;
  247. /* if the device is ARM only, return */
  248. if ((REG(CHIP_REV_ID_REG) & 0x3f) == 0x10)
  249. return;
  250. if (!strcmp(getenv("dspwake"), "no"))
  251. return;
  252. *resetvect++ = 0x1E000; /* DSP Idle */
  253. /* clear out the next 10 words as NOP */
  254. memset(resetvect, 0, sizeof(unsigned) * 10);
  255. /* setup the DSP reset vector */
  256. REG(HOST1CFG) = DAVINCI_L3CBARAM_BASE;
  257. dsp_lpsc_on(1, DAVINCI_LPSC_GEM);
  258. REG(PSC0_MDCTL + (15 * 4)) |= 0x100;
  259. }
  260. #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
  261. /**
  262. * rmii_hw_init
  263. *
  264. */
  265. int rmii_hw_init(void)
  266. {
  267. return 0;
  268. }
  269. #endif /* CONFIG_DRIVER_TI_EMAC_USE_RMII */
  270. int misc_init_r(void)
  271. {
  272. uint8_t tmp[20], addr[10];
  273. if (getenv("ethaddr") == NULL) {
  274. /* Read Ethernet MAC address from EEPROM */
  275. if (dvevm_read_mac_address(addr)) {
  276. /* Set Ethernet MAC address from EEPROM */
  277. davinci_sync_env_enetaddr(addr);
  278. } else {
  279. get_mac_addr(addr);
  280. }
  281. if (!is_multicast_ethaddr(addr) && !is_zero_ethaddr(addr)) {
  282. sprintf((char *)tmp, "%02x:%02x:%02x:%02x:%02x:%02x",
  283. addr[0], addr[1], addr[2], addr[3], addr[4],
  284. addr[5]);
  285. setenv("ethaddr", (char *)tmp);
  286. } else {
  287. printf("Invalid MAC address read.\n");
  288. }
  289. }
  290. #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
  291. /* Select RMII fucntion through the expander */
  292. if (rmii_hw_init())
  293. printf("RMII hardware init failed!!!\n");
  294. #endif
  295. dspwake();
  296. return 0;
  297. }
  298. #ifdef CONFIG_DAVINCI_MMC
  299. static struct davinci_mmc mmc_sd0 = {
  300. .reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE,
  301. .host_caps = MMC_MODE_4BIT, /* DA850 supports only 4-bit SD/MMC */
  302. .voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
  303. .version = MMC_CTLR_VERSION_2,
  304. };
  305. int board_mmc_init(bd_t *bis)
  306. {
  307. mmc_sd0.input_clk = clk_get(DAVINCI_MMCSD_CLKID);
  308. /* Add slot-0 to mmc subsystem */
  309. return davinci_mmc_init(bis, &mmc_sd0);
  310. }
  311. #endif