chip_config.c 2.5 KB

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  1. /*
  2. * (C) Copyright 2009
  3. * Stefan Roese, DENX Software Engineering, sr@denx.de.
  4. *
  5. * SPDX-License-Identifier: GPL-2.0+
  6. */
  7. #include <common.h>
  8. #include <asm/ppc4xx_config.h>
  9. struct ppc4xx_config ppc4xx_config_val[] = {
  10. {
  11. "333-133-nor", "NOR CPU: 333 PLB: 133 OPB: 66 EBC: 66",
  12. {
  13. 0x84, 0x70, 0xa2, 0xa6, 0x05, 0x57, 0xa0, 0x10,
  14. 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
  15. }
  16. },
  17. {
  18. "333-166-nor", "NOR CPU: 333 PLB: 166 OPB: 83 EBC: 55",
  19. {
  20. 0xc7, 0x78, 0xf3, 0x4e, 0x05, 0xd7, 0xa0, 0x30,
  21. 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
  22. }
  23. },
  24. {
  25. "333-166-nand", "NAND CPU: 333 PLB: 166 OPB: 83 EBC: 55",
  26. {
  27. 0xc7, 0x78, 0xf3, 0x4e, 0x05, 0xd7, 0xd0, 0x30,
  28. 0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
  29. }
  30. },
  31. {
  32. "400-133-nor", "NOR CPU: 400 PLB: 133 OPB: 66 EBC: 66",
  33. {
  34. 0x86, 0x78, 0xc2, 0xc6, 0x05, 0x57, 0xa0, 0x30,
  35. 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
  36. }
  37. },
  38. {
  39. "400-160-nor", "NOR CPU: 400 PLB: 160 OPB: 80 EBC: 53",
  40. {
  41. 0x86, 0x78, 0xc2, 0xa6, 0x05, 0xd7, 0xa0, 0x10,
  42. 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
  43. }
  44. },
  45. {
  46. "416-166-nor", "NOR CPU: 416 PLB: 166 OPB: 83 EBC: 55",
  47. {
  48. 0xc6, 0x78, 0x52, 0xa6, 0x05, 0xd7, 0xa0, 0x10,
  49. 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
  50. }
  51. },
  52. {
  53. "416-166-nand", "NAND CPU: 416 PLB: 166 OPB: 83 EBC: 55",
  54. {
  55. 0xc6, 0x78, 0x52, 0xa6, 0x05, 0xd7, 0xd0, 0x10,
  56. 0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
  57. }
  58. },
  59. {
  60. "500-166-nor", "NOR CPU: 500 PLB: 166 OPB: 83 EBC: 55",
  61. {
  62. 0xc7, 0x78, 0x52, 0xc6, 0x05, 0xd7, 0xa0, 0x30,
  63. 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
  64. }
  65. },
  66. {
  67. "500-166-nand", "NAND CPU: 500 PLB: 166 OPB: 83 EBC: 55",
  68. {
  69. 0xc7, 0x78, 0x52, 0xc6, 0x05, 0xd7, 0xd0, 0x30,
  70. 0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
  71. }
  72. },
  73. {
  74. "533-133-nor", "NOR CPU: 533 PLB: 133 OPB: 66 EBC: 66",
  75. {
  76. 0x87, 0x78, 0x82, 0x52, 0x09, 0x57, 0xa0, 0x30,
  77. 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
  78. }
  79. },
  80. {
  81. "667-133-nor", "NOR CPU: 667 PLB: 133 OPB: 66 EBC: 66",
  82. {
  83. 0x87, 0x78, 0xa2, 0x56, 0x09, 0x57, 0xa0, 0x30,
  84. 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
  85. }
  86. },
  87. {
  88. "667-166-nor", "NOR CPU: 667 PLB: 166 OPB: 83 EBC: 55",
  89. {
  90. 0x87, 0x78, 0xa2, 0x52, 0x09, 0xd7, 0xa0, 0x30,
  91. 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
  92. }
  93. },
  94. {
  95. "667-166-nand", "NAND CPU: 667 PLB: 166 OPB: 83 EBC: 55",
  96. {
  97. 0x87, 0x78, 0xa2, 0x52, 0x09, 0xd7, 0xd0, 0x30,
  98. 0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
  99. }
  100. },
  101. };
  102. int ppc4xx_config_count = ARRAY_SIZE(ppc4xx_config_val);