chromebox_panther.dts 1.5 KB

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  1. /dts-v1/;
  2. /include/ "skeleton.dtsi"
  3. /include/ "serial.dtsi"
  4. /include/ "rtc.dtsi"
  5. /include/ "tsc_timer.dtsi"
  6. /include/ "coreboot_fb.dtsi"
  7. / {
  8. model = "Google Panther";
  9. compatible = "google,panther", "intel,haswell";
  10. aliases {
  11. spi0 = &spi;
  12. };
  13. config {
  14. silent-console = <0>;
  15. no-keyboard;
  16. };
  17. chosen {
  18. stdout-path = "/serial";
  19. };
  20. pci {
  21. compatible = "pci-x86";
  22. #address-cells = <3>;
  23. #size-cells = <2>;
  24. u-boot,dm-pre-reloc;
  25. ranges = <0x02000000 0x0 0xe0000000 0xe0000000 0 0x10000000
  26. 0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
  27. 0x01000000 0x0 0x1000 0x1000 0 0xf000>;
  28. pch@1f,0 {
  29. reg = <0x0000f800 0 0 0 0>;
  30. compatible = "intel,pch9";
  31. #address-cells = <1>;
  32. #size-cells = <1>;
  33. spi: spi {
  34. #address-cells = <1>;
  35. #size-cells = <0>;
  36. compatible = "intel,ich9-spi";
  37. spi-flash@0 {
  38. #size-cells = <1>;
  39. #address-cells = <1>;
  40. reg = <0>;
  41. compatible = "winbond,w25q64",
  42. "spi-flash";
  43. memory-map = <0xff800000 0x00800000>;
  44. rw-mrc-cache {
  45. label = "rw-mrc-cache";
  46. reg = <0x003e0000 0x00010000>;
  47. };
  48. };
  49. };
  50. gpioa {
  51. compatible = "intel,ich6-gpio";
  52. u-boot,dm-pre-reloc;
  53. reg = <0 0x10>;
  54. bank-name = "A";
  55. };
  56. gpiob {
  57. compatible = "intel,ich6-gpio";
  58. u-boot,dm-pre-reloc;
  59. reg = <0x30 0x10>;
  60. bank-name = "B";
  61. };
  62. gpioc {
  63. compatible = "intel,ich6-gpio";
  64. u-boot,dm-pre-reloc;
  65. reg = <0x40 0x10>;
  66. bank-name = "C";
  67. };
  68. };
  69. };
  70. tpm {
  71. reg = <0xfed40000 0x5000>;
  72. compatible = "infineon,slb9635lpc";
  73. };
  74. };