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ppc440.h

ppc440.h 5.2 KB
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  1. /*
    2. 

  2.  * (C) Copyright 2006
    3. 

  3.  * Sylvie Gohl,             AMCC/IBM, gohl.sylvie@fr.ibm.com
    4. 

  4.  * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
    5. 

  5.  * Thierry Roman,           AMCC/IBM, thierry_roman@fr.ibm.com
    6. 

  6.  * Alain Saurel,            AMCC/IBM, alain.saurel@fr.ibm.com
    7. 

  7.  * Robert Snyder,           AMCC/IBM, rob.snyder@fr.ibm.com
    8. 

  8.  *
    9. 

  9.  * (C) Copyright 2010
    10. 

  10.  * Stefan Roese, DENX Software Engineering, sr@denx.de.
    11. 

  11.  *
    12. 

  12.  * SPDX-License-Identifier:	GPL-2.0	IBM-pibs
    13. 

  13.  */
    14. 

  14. 

  15. #ifndef __PPC440_H__
    16. 

  16. #define __PPC440_H__
    17. 

  17. 

  18. #define CONFIG_SYS_DCACHE_SIZE		(32 << 10)	/* For AMCC 440 CPUs */
    19. 

  19. 

  20. /*
    21. 

  21.  * DCRs & Related
    22. 

  22.  */
    23. 

  23. 

  24. /* Memory mapped registers */
    25. 

  25. #define PCIL0_CFGADR	(CONFIG_SYS_PCI_BASE + 0x0ec00000)
    26. 

  26. #define PCIL0_CFGDATA	(CONFIG_SYS_PCI_BASE + 0x0ec00004)
    27. 

  27. #define PCIL0_CFGBASE	(CONFIG_SYS_PCI_BASE + 0x0ec80000)
    28. 

  28. #define PCIL0_IOBASE	(CONFIG_SYS_PCI_BASE + 0x08000000)
    29. 

  29. 

  30. /* DCR registers */
    31. 

  31. 

  32. /* CPR register declarations */
    33. 

  33. #define CPR0_PLLC	0x0040
    34. 

  34. #define CPR0_PLLD	0x0060
    35. 

  35. #define CPR0_PRIMAD0	0x0080
    36. 

  36. #define CPR0_PRIMBD0	0x00a0
    37. 

  37. #define CPR0_OPBD0	0x00c0
    38. 

  38. #define CPR0_PERD	0x00e0
    39. 

  39. #define CPR0_MALD	0x0100
    40. 

  40. #define CPR0_SPCID	0x0120
    41. 

  41. #define CPR0_ICFG	0x0140
    42. 

  42. 

  43. /* SDR register definations */
    44. 

  44. #define SDR0_SDSTP0	0x0020
    45. 

  45. #define SDR0_SDSTP1	0x0021
    46. 

  46. #define SDR0_PINSTP	0x0040
    47. 

  47. #define SDR0_SDCS0	0x0060
    48. 

  48. #define SDR0_ECID0	0x0080
    49. 

  49. #define SDR0_ECID1	0x0081
    50. 

  50. #define SDR0_ECID2	0x0082
    51. 

  51. #define SDR0_ECID3	0x0083
    52. 

  52. #define SDR0_DDR0	0x00e1
    53. 

  53. #define SDR0_EBC	0x0100
    54. 

  54. #define SDR0_UART0	0x0120
    55. 

  55. #define SDR0_UART1	0x0121
    56. 

  56. #define SDR0_UART2	0x0122
    57. 

  57. #define SDR0_UART3	0x0123
    58. 

  58. #define SDR0_CP440	0x0180
    59. 

  59. #define SDR0_XCR	0x01c0
    60. 

  60. #define SDR0_XCR0	0x01c0
    61. 

  61. #define SDR0_XPLLC	0x01c1
    62. 

  62. #define SDR0_XPLLD	0x01c2
    63. 

  63. #define SDR0_SRST	0x0200
    64. 

  64. #define SDR0_SRST0	SDR0_SRST
    65. 

  65. #define SDR0_SRST1	0x0201
    66. 

  66. #define SDR0_AMP0	0x0240
    67. 

  67. #define SDR0_AMP1	0x0241
    68. 

  68. #define SDR0_USB0	0x0320
    69. 

  69. #define SDR0_CUST0	0x4000
    70. 

  70. #define SDR0_CUST1	0x4002
    71. 

  71. #define SDR0_CUST2	0x4004
    72. 

  72. #define SDR0_CUST3	0x4006
    73. 

  73. #define SDR0_PFC0	0x4100
    74. 

  74. #define SDR0_PFC1	0x4101
    75. 

  75. #define SDR0_PFC2   	0x4102
    76. 

  76. #define SDR0_PFC4	0x4104
    77. 

  77. #define SDR0_MFR	0x4300
    78. 

  78. 

  79. #define SDR0_DDR0_DDRM_DECODE(n)	((((u32)(n)) >> 29) & 0x03)
    80. 

  80. 

  81. #define SDR0_PCI0_PAE_MASK		(0x80000000 >> 0)
    82. 

  82. #define SDR0_XCR0_PAE_MASK		(0x80000000 >> 0)
    83. 

  83. 

  84. #define SDR0_PFC0_GEIE_MASK		0x00003e00
    85. 

  85. #define SDR0_PFC0_GEIE_TRE		0x00003e00
    86. 

  86. #define SDR0_PFC0_GEIE_NOTRE		0x00000000
    87. 

  87. #define SDR0_PFC0_TRE_MASK		(0x80000000 >> 23)
    88. 

  88. #define SDR0_PFC0_TRE_DISABLE		0x00000000
    89. 

  89. #define SDR0_PFC0_TRE_ENABLE		(0x80000000 >> 23)
    90. 

  90. 

  91. /*
    92. 

  92.  * Core Configuration/MMU configuration for 440
    93. 

  93.  */
    94. 

  94. #define CCR0_DAPUIB		0x00100000
    95. 

  95. #define CCR0_DTB		0x00008000
    96. 

  96. 

  97. #define SDR0_SDCS_SDD		(0x80000000 >> 31)
    98. 

  98. 

  99. /* todo: move this code from macro offsets to struct */
    100. 

  100. #define PCIL0_VENDID		(PCIL0_CFGBASE + PCI_VENDOR_ID )
    101. 

  101. #define PCIL0_DEVID		(PCIL0_CFGBASE + PCI_DEVICE_ID )
    102. 

  102. #define PCIL0_CMD		(PCIL0_CFGBASE + PCI_COMMAND )
    103. 

  103. #define PCIL0_STATUS		(PCIL0_CFGBASE + PCI_STATUS )
    104. 

  104. #define PCIL0_REVID		(PCIL0_CFGBASE + PCI_REVISION_ID )
    105. 

  105. #define PCIL0_CLS		(PCIL0_CFGBASE + PCI_CLASS_CODE)
    106. 

  106. #define PCIL0_CACHELS		(PCIL0_CFGBASE + PCI_CACHE_LINE_SIZE )
    107. 

  107. #define PCIL0_LATTIM		(PCIL0_CFGBASE + PCI_LATENCY_TIMER )
    108. 

  108. #define PCIL0_HDTYPE		(PCIL0_CFGBASE + PCI_HEADER_TYPE )
    109. 

  109. #define PCIL0_BIST		(PCIL0_CFGBASE + PCI_BIST )
    110. 

  110. #define PCIL0_BAR0		(PCIL0_CFGBASE + PCI_BASE_ADDRESS_0 )
    111. 

  111. #define PCIL0_BAR1		(PCIL0_CFGBASE + PCI_BASE_ADDRESS_1 )
    112. 

  112. #define PCIL0_BAR2		(PCIL0_CFGBASE + PCI_BASE_ADDRESS_2 )
    113. 

  113. #define PCIL0_BAR3		(PCIL0_CFGBASE + PCI_BASE_ADDRESS_3 )
    114. 

  114. #define PCIL0_BAR4		(PCIL0_CFGBASE + PCI_BASE_ADDRESS_4 )
    115. 

  115. #define PCIL0_BAR5		(PCIL0_CFGBASE + PCI_BASE_ADDRESS_5 )
    116. 

  116. #define PCIL0_CISPTR		(PCIL0_CFGBASE + PCI_CARDBUS_CIS )
    117. 

  117. #define PCIL0_SBSYSVID		(PCIL0_CFGBASE + PCI_SUBSYSTEM_VENDOR_ID )
    118. 

  118. #define PCIL0_SBSYSID		(PCIL0_CFGBASE + PCI_SUBSYSTEM_ID )
    119. 

  119. #define PCIL0_EROMBA		(PCIL0_CFGBASE + PCI_ROM_ADDRESS )
    120. 

  120. #define PCIL0_CAP		(PCIL0_CFGBASE + PCI_CAPABILITY_LIST )
    121. 

  121. #define PCIL0_RES0		(PCIL0_CFGBASE + 0x0035 )
    122. 

  122. #define PCIL0_RES1		(PCIL0_CFGBASE + 0x0036 )
    123. 

  123. #define PCIL0_RES2		(PCIL0_CFGBASE + 0x0038 )
    124. 

  124. #define PCIL0_INTLN		(PCIL0_CFGBASE + PCI_INTERRUPT_LINE )
    125. 

  125. #define PCIL0_INTPN		(PCIL0_CFGBASE + PCI_INTERRUPT_PIN )
    126. 

  126. 

  127. #define PCIL0_MINGNT		(PCIL0_CFGBASE + PCI_MIN_GNT )
    128. 

  128. #define PCIL0_MAXLTNCY		(PCIL0_CFGBASE + PCI_MAX_LAT )
    129. 

  129. 

  130. #define PCIL0_POM0LAL		(PCIL0_CFGBASE + 0x0068)
    131. 

  131. #define PCIL0_POM0LAH		(PCIL0_CFGBASE + 0x006c)
    132. 

  132. #define PCIL0_POM0SA		(PCIL0_CFGBASE + 0x0070)
    133. 

  133. #define PCIL0_POM0PCIAL		(PCIL0_CFGBASE + 0x0074)
    134. 

  134. #define PCIL0_POM0PCIAH		(PCIL0_CFGBASE + 0x0078)
    135. 

  135. #define PCIL0_POM1LAL		(PCIL0_CFGBASE + 0x007c)
    136. 

  136. #define PCIL0_POM1LAH		(PCIL0_CFGBASE + 0x0080)
    137. 

  137. #define PCIL0_POM1SA		(PCIL0_CFGBASE + 0x0084)
    138. 

  138. #define PCIL0_POM1PCIAL		(PCIL0_CFGBASE + 0x0088)
    139. 

  139. #define PCIL0_POM1PCIAH		(PCIL0_CFGBASE + 0x008c)
    140. 

  140. #define PCIL0_POM2SA		(PCIL0_CFGBASE + 0x0090)
    141. 

  141. 

  142. #define PCIL0_PIM0SA		(PCIL0_CFGBASE + 0x0098)
    143. 

  143. #define PCIL0_PIM0LAL		(PCIL0_CFGBASE + 0x009c)
    144. 

  144. #define PCIL0_PIM0LAH		(PCIL0_CFGBASE + 0x00a0)
    145. 

  145. #define PCIL0_PIM1SA		(PCIL0_CFGBASE + 0x00a4)
    146. 

  146. #define PCIL0_PIM1LAL		(PCIL0_CFGBASE + 0x00a8)
    147. 

  147. #define PCIL0_PIM1LAH		(PCIL0_CFGBASE + 0x00ac)
    148. 

  148. #define PCIL0_PIM2SA		(PCIL0_CFGBASE + 0x00b0)
    149. 

  149. #define PCIL0_PIM2LAL		(PCIL0_CFGBASE + 0x00b4)
    150. 

  150. #define PCIL0_PIM2LAH		(PCIL0_CFGBASE + 0x00b8)
    151. 

  151. 

  152. #define PCIL0_STS		(PCIL0_CFGBASE + 0x00e0)
    153. 

  153. 

  154. #endif	/* __PPC440_H__ */
    155.