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u-boot-2017.01+gitAUTOINC+340fb36f04-g340fb36f04
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asm
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ppc405.h

ppc405.h 2.3 KB
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  1. /*
    2. 

  2.  * SPDX-License-Identifier:	GPL-2.0	IBM-pibs
    3. 

  3.  */
    4. 

  4. 

  5. #ifndef	__PPC405_H__
    6. 

  6. #define __PPC405_H__
    7. 

  7. 

  8. /* Define bits and masks for real-mode storage attribute control registers */
    9. 

  9. #define PPC_128MB_SACR_BIT(addr)	((addr) >> 27)
    10. 

  10. #define PPC_128MB_SACR_VALUE(addr)	PPC_REG_VAL(PPC_128MB_SACR_BIT(addr),1)
    11. 

  11. 

  12. #define CONFIG_SYS_DCACHE_SIZE		(16 << 10)	/* For AMCC 405 CPUs */
    13. 

  13. 

  14. /* DCR registers */
    15. 

  15. #define PLB0_ACR	0x0087
    16. 

  16. 

  17. /* SDR registers */
    18. 

  18. #define SDR0_PINSTP	0x0040
    19. 

  19. 

  20. /* CPR registers */
    21. 

  21. #define CPR0_CLKUPD	0x0020
    22. 

  22. #define CPR0_PLLC	0x0040
    23. 

  23. #define CPR0_PLLD	0x0060
    24. 

  24. #define CPR0_CPUD	0x0080
    25. 

  25. #define CPR0_PLBD	0x00a0
    26. 

  26. #define CPR0_OPBD0	0x00c0
    27. 

  27. #define CPR0_PERD	0x00e0
    28. 

  28. 

  29. /*
    30. 

  30.  * DMA
    31. 

  31.  */
    32. 

  32. #define DMA_DCR_BASE	0x0100
    33. 

  33. #define DMACR0		(DMA_DCR_BASE + 0x00)  /* DMA channel control reg 0	*/
    34. 

  34. #define DMACT0		(DMA_DCR_BASE + 0x01)  /* DMA count reg 0		*/
    35. 

  35. #define DMADA0		(DMA_DCR_BASE + 0x02)  /* DMA destination address reg 0 */
    36. 

  36. #define DMASA0		(DMA_DCR_BASE + 0x03)  /* DMA source address reg 0	*/
    37. 

  37. #define DMASB0		(DMA_DCR_BASE + 0x04)  /* DMA sg descriptor addr 0	*/
    38. 

  38. #define DMACR1		(DMA_DCR_BASE + 0x08)  /* DMA channel control reg 1	*/
    39. 

  39. #define DMACT1		(DMA_DCR_BASE + 0x09)  /* DMA count reg 1		*/
    40. 

  40. #define DMADA1		(DMA_DCR_BASE + 0x0a)  /* DMA destination address reg 1 */
    41. 

  41. #define DMASA1		(DMA_DCR_BASE + 0x0b)  /* DMA source address reg 1	*/
    42. 

  42. #define DMASB1		(DMA_DCR_BASE + 0x0c)  /* DMA sg descriptor addr 1	*/
    43. 

  43. #define DMACR2		(DMA_DCR_BASE + 0x10)  /* DMA channel control reg 2	*/
    44. 

  44. #define DMACT2		(DMA_DCR_BASE + 0x11)  /* DMA count reg 2		*/
    45. 

  45. #define DMADA2		(DMA_DCR_BASE + 0x12)  /* DMA destination address reg 2 */
    46. 

  46. #define DMASA2		(DMA_DCR_BASE + 0x13)  /* DMA source address reg 2	*/
    47. 

  47. #define DMASB2		(DMA_DCR_BASE + 0x14)  /* DMA sg descriptor addr 2	*/
    48. 

  48. #define DMACR3		(DMA_DCR_BASE + 0x18)  /* DMA channel control reg 3	*/
    49. 

  49. #define DMACT3		(DMA_DCR_BASE + 0x19)  /* DMA count reg 3		*/
    50. 

  50. #define DMADA3		(DMA_DCR_BASE + 0x1a)  /* DMA destination address reg 3 */
    51. 

  51. #define DMASA3		(DMA_DCR_BASE + 0x1b)  /* DMA source address reg 3	*/
    52. 

  52. #define DMASB3		(DMA_DCR_BASE + 0x1c)  /* DMA sg descriptor addr 3	*/
    53. 

  53. #define DMASR		(DMA_DCR_BASE + 0x20)  /* DMA status reg		*/
    54. 

  54. #define DMASGC		(DMA_DCR_BASE + 0x23)  /* DMA scatter/gather command reg*/
    55. 

  55. #define DMAADR		(DMA_DCR_BASE + 0x24)  /* DMA address decode reg	*/
    56. 

  56. 

  57. #endif	/* __PPC405_H__ */
    58.