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u-boot-2017.01+gitAUTOINC+340fb36f04-g340fb36f04
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arch
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powerpc
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cpu
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mpc8260
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kgdb.S

kgdb.S 890 B
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  1. /*
    2. 

  2.  *  Copyright (C) 2000	Murray Jensen <Murray.Jensen@cmst.csiro.au>
    3. 

  3.  *
    4. 

  4.  * SPDX-License-Identifier:	GPL-2.0+
    5. 

  5.  */
    6. 

  6. 

  7. #include <config.h>
    8. 

  8. #include <command.h>
    9. 

  9. #include <mpc8260.h>
    10. 

  10. 

  11. #include <ppc_asm.tmpl>
    12. 

  12. #include <ppc_defs.h>
    13. 

  13. 

  14. #include <asm/cache.h>
    15. 

  15. #include <asm/mmu.h>
    16. 

  16. 

  17. #if defined(CONFIG_CMD_KGDB)
    18. 

  18. 

  19.  /*
    20. 

  20.  * cache flushing routines for kgdb
    21. 

  21.  */
    22. 

  22. 

  23. 	.globl	kgdb_flush_cache_all
    24. 

  24. kgdb_flush_cache_all:
    25. 

  25. 	mfspr	r3, HID0
    26. 

  26. 	ori	r3, r3, HID0_ICFI|HID0_DCI	/* Invalidate All */
    27. 

  27. 	SYNC
    28. 

  28. 	mtspr	HID0, r3
    29. 

  29. 	blr
    30. 

  30. 

  31. 	.globl	kgdb_flush_cache_range
    32. 

  32. kgdb_flush_cache_range:
    33. 

  33. 	li	r5,CONFIG_SYS_CACHELINE_SIZE-1
    34. 

  34. 	andc	r3,r3,r5
    35. 

  35. 	subf	r4,r3,r4
    36. 

  36. 	add	r4,r4,r5
    37. 

  37. 	srwi.	r4,r4,CONFIG_SYS_CACHELINE_SHIFT
    38. 

  38. 	beqlr
    39. 

  39. 	mtctr	r4
    40. 

  40. 	mr	r6,r3
    41. 

  41. 1:	dcbst	0,r3
    42. 

  42. 	addi	r3,r3,CONFIG_SYS_CACHELINE_SIZE
    43. 

  43. 	bdnz	1b
    44. 

  44. 	sync				/* wait for dcbst's to get to ram */
    45. 

  45. 	mtctr	r4
    46. 

  46. 2:	icbi	0,r6
    47. 

  47. 	addi	r6,r6,CONFIG_SYS_CACHELINE_SIZE
    48. 

  48. 	bdnz	2b
    49. 

  49. 	SYNC
    50. 

  50. 	blr
    51. 

  51. 

  52. #endif
    53.