board_init.c 3.7 KB

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  1. /*
  2. * Copyright (C) 2012-2015 Panasonic Corporation
  3. * Copyright (C) 2015-2016 Socionext Inc.
  4. * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  5. *
  6. * SPDX-License-Identifier: GPL-2.0+
  7. */
  8. #include <common.h>
  9. #include <libfdt.h>
  10. #include <linux/io.h>
  11. #include "init.h"
  12. #include "micro-support-card.h"
  13. #include "sg-regs.h"
  14. #include "soc-info.h"
  15. DECLARE_GLOBAL_DATA_PTR;
  16. static void uniphier_setup_xirq(void)
  17. {
  18. const void *fdt = gd->fdt_blob;
  19. int soc_node, aidet_node;
  20. const u32 *val;
  21. unsigned long aidet_base;
  22. u32 tmp;
  23. soc_node = fdt_path_offset(fdt, "/soc");
  24. if (soc_node < 0)
  25. return;
  26. aidet_node = fdt_subnode_offset_namelen(fdt, soc_node, "aidet", 5);
  27. if (aidet_node < 0)
  28. return;
  29. val = fdt_getprop(fdt, aidet_node, "reg", NULL);
  30. if (!val)
  31. return;
  32. aidet_base = fdt32_to_cpu(*val);
  33. tmp = readl(aidet_base + 8); /* AIDET DETCONFR2 */
  34. tmp |= 0x00ff0000; /* Set XIRQ0-7 low active */
  35. writel(tmp, aidet_base + 8);
  36. tmp = readl(0x55000090); /* IRQCTL */
  37. tmp |= 0x000000ff;
  38. writel(tmp, 0x55000090);
  39. }
  40. static void uniphier_nand_pin_init(bool cs2)
  41. {
  42. #ifdef CONFIG_NAND_DENALI
  43. if (uniphier_pin_init(cs2 ? "nand2cs_grp" : "nand_grp"))
  44. pr_err("failed to init NAND pins\n");
  45. #endif
  46. }
  47. int board_init(void)
  48. {
  49. const struct uniphier_board_data *bd;
  50. led_puts("U0");
  51. bd = uniphier_get_board_param();
  52. if (!bd)
  53. return -ENODEV;
  54. switch (uniphier_get_soc_type()) {
  55. #if defined(CONFIG_ARCH_UNIPHIER_SLD3)
  56. case SOC_UNIPHIER_SLD3:
  57. uniphier_nand_pin_init(true);
  58. led_puts("U1");
  59. uniphier_sld3_pll_init();
  60. uniphier_ld4_clk_init();
  61. break;
  62. #endif
  63. #if defined(CONFIG_ARCH_UNIPHIER_LD4)
  64. case SOC_UNIPHIER_LD4:
  65. uniphier_nand_pin_init(true);
  66. led_puts("U1");
  67. uniphier_ld4_pll_init();
  68. uniphier_ld4_clk_init();
  69. break;
  70. #endif
  71. #if defined(CONFIG_ARCH_UNIPHIER_PRO4)
  72. case SOC_UNIPHIER_PRO4:
  73. uniphier_nand_pin_init(false);
  74. led_puts("U1");
  75. uniphier_pro4_pll_init();
  76. uniphier_pro4_clk_init();
  77. break;
  78. #endif
  79. #if defined(CONFIG_ARCH_UNIPHIER_SLD8)
  80. case SOC_UNIPHIER_SLD8:
  81. uniphier_nand_pin_init(true);
  82. led_puts("U1");
  83. uniphier_ld4_pll_init();
  84. uniphier_ld4_clk_init();
  85. break;
  86. #endif
  87. #if defined(CONFIG_ARCH_UNIPHIER_PRO5)
  88. case SOC_UNIPHIER_PRO5:
  89. uniphier_nand_pin_init(true);
  90. led_puts("U1");
  91. uniphier_pro5_clk_init();
  92. break;
  93. #endif
  94. #if defined(CONFIG_ARCH_UNIPHIER_PXS2)
  95. case SOC_UNIPHIER_PXS2:
  96. uniphier_nand_pin_init(true);
  97. led_puts("U1");
  98. uniphier_pxs2_clk_init();
  99. break;
  100. #endif
  101. #if defined(CONFIG_ARCH_UNIPHIER_LD6B)
  102. case SOC_UNIPHIER_LD6B:
  103. uniphier_nand_pin_init(true);
  104. led_puts("U1");
  105. uniphier_pxs2_clk_init();
  106. break;
  107. #endif
  108. #if defined(CONFIG_ARCH_UNIPHIER_LD11)
  109. case SOC_UNIPHIER_LD11:
  110. uniphier_nand_pin_init(false);
  111. sg_set_pinsel(149, 14, 8, 4); /* XIRQ0 -> XIRQ0 */
  112. sg_set_iectrl(149);
  113. sg_set_pinsel(153, 14, 8, 4); /* XIRQ4 -> XIRQ4 */
  114. sg_set_iectrl(153);
  115. led_puts("U1");
  116. uniphier_ld11_pll_init();
  117. uniphier_ld11_clk_init();
  118. break;
  119. #endif
  120. #if defined(CONFIG_ARCH_UNIPHIER_LD20)
  121. case SOC_UNIPHIER_LD20:
  122. /* ES1 errata: increase VDD09 supply to suppress VBO noise */
  123. if (uniphier_get_soc_revision() == 1) {
  124. writel(0x00000003, 0x6184e004);
  125. writel(0x00000100, 0x6184e040);
  126. writel(0x0000b500, 0x6184e024);
  127. writel(0x00000001, 0x6184e000);
  128. }
  129. uniphier_nand_pin_init(false);
  130. sg_set_pinsel(149, 14, 8, 4); /* XIRQ0 -> XIRQ0 */
  131. sg_set_iectrl(149);
  132. sg_set_pinsel(153, 14, 8, 4); /* XIRQ4 -> XIRQ4 */
  133. sg_set_iectrl(153);
  134. led_puts("U1");
  135. uniphier_ld20_pll_init(bd);
  136. uniphier_ld20_clk_init();
  137. cci500_init(2);
  138. break;
  139. #endif
  140. default:
  141. break;
  142. }
  143. uniphier_setup_xirq();
  144. led_puts("U2");
  145. support_card_late_init();
  146. led_puts("U3");
  147. #ifdef CONFIG_ARM64
  148. uniphier_smp_kick_all_cpus();
  149. #endif
  150. led_puts("Uboo");
  151. return 0;
  152. }