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u-boot-2017.01+gitAUTOINC+340fb36f04-g340fb36f04
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arch
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arm
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include
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asm
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assembler.h

assembler.h 2.0 KB
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  1. /*
    2. 

  2.  *  arch/arm/include/asm/assembler.h
    3. 

  3.  *
    4. 

  4.  *  Copyright (C) 1996-2000 Russell King
    5. 

  5.  *
    6. 

  6.  * This program is free software; you can redistribute it and/or modify
    7. 

  7.  * it under the terms of the GNU General Public License version 2 as
    8. 

  8.  * published by the Free Software Foundation.
    9. 

  9.  *
    10. 

  10.  *  This file contains arm architecture specific defines
    11. 

  11.  *  for the different processors.
    12. 

  12.  *
    13. 

  13.  *  Do not include any C declarations in this file - it is included by
    14. 

  14.  *  assembler source.
    15. 

  15.  */
    16. 

  16. 

  17. #include <config.h>
    18. 

  18. #include <asm/unified.h>
    19. 

  19. 

  20. /*
    21. 

  21.  * Endian independent macros for shifting bytes within registers.
    22. 

  22.  */
    23. 

  23. #ifndef __ARMEB__
    24. 

  24. #define lspull		lsr
    25. 

  25. #define lspush		lsl
    26. 

  26. #define get_byte_0	lsl #0
    27. 

  27. #define get_byte_1	lsr #8
    28. 

  28. #define get_byte_2	lsr #16
    29. 

  29. #define get_byte_3	lsr #24
    30. 

  30. #define put_byte_0	lsl #0
    31. 

  31. #define put_byte_1	lsl #8
    32. 

  32. #define put_byte_2	lsl #16
    33. 

  33. #define put_byte_3	lsl #24
    34. 

  34. #else
    35. 

  35. #define lspull		lsl
    36. 

  36. #define lspush		lsr
    37. 

  37. #define get_byte_0	lsr #24
    38. 

  38. #define get_byte_1	lsr #16
    39. 

  39. #define get_byte_2	lsr #8
    40. 

  40. #define get_byte_3      lsl #0
    41. 

  41. #define put_byte_0	lsl #24
    42. 

  42. #define put_byte_1	lsl #16
    43. 

  43. #define put_byte_2	lsl #8
    44. 

  44. #define put_byte_3      lsl #0
    45. 

  45. #endif
    46. 

  46. 

  47. /*
    48. 

  48.  * Data preload for architectures that support it
    49. 

  49.  */
    50. 

  50. #if defined(__ARM_ARCH_5E__) || defined(__ARM_ARCH_5TE__) || \
    51. 

  51. 	defined(__ARM_ARCH_6__) || defined(__ARM_ARCH_6J__) || \
    52. 

  52. 	defined(__ARM_ARCH_6T2__) || defined(__ARM_ARCH_6Z__) || \
    53. 

  53. 	defined(__ARM_ARCH_6ZK__) || defined(__ARM_ARCH_7A__) || \
    54. 

  54. 	defined(__ARM_ARCH_7R__)
    55. 

  55. #define PLD(code...)	code
    56. 

  56. #else
    57. 

  57. #define PLD(code...)
    58. 

  58. #endif
    59. 

  59. 

  60. 	.irp	c,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,hs,lo
    61. 

  61. 	.macro	ret\c, reg
    62. 

  62. #if defined(__ARM_ARCH_5E__) || defined(__ARM_ARCH_5TE__)
    63. 

  63. 	mov\c	pc, \reg
    64. 

  64. #else
    65. 

  65. 	.ifeqs	"\reg", "lr"
    66. 

  66. 	bx\c	\reg
    67. 

  67. 	.else
    68. 

  68. 	mov\c	pc, \reg
    69. 

  69. 	.endif
    70. 

  70. #endif
    71. 

  71. 	.endm
    72. 

  72. 	.endr
    73. 

  73. 

  74. /*
    75. 

  75.  * Cache aligned, used for optimized memcpy/memset
    76. 

  76.  * In the kernel this is only enabled for Feroceon CPU's...
    77. 

  77.  * We disable it especially for Thumb builds since those instructions
    78. 

  78.  * are not made in a Thumb ready way...
    79. 

  79.  */
    80. 

  80. #ifdef CONFIG_SYS_THUMB_BUILD
    81. 

  81. #define CALGN(code...)
    82. 

  82. #else
    83. 

  83. #define CALGN(code...) code
    84. 

  84. #endif
    85.