start.S 2.4 KB

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  1. /*
  2. * armboot - Startup Code for ARM926EJS CPU-core
  3. *
  4. * Copyright (c) 2003 Texas Instruments
  5. *
  6. * ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
  7. *
  8. * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
  9. * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
  10. * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
  11. * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
  12. * Copyright (c) 2003 Kshitij <kshitij@ti.com>
  13. * Copyright (c) 2010 Albert Aribaud <albert.u.boot@aribaud.net>
  14. *
  15. * SPDX-License-Identifier: GPL-2.0+
  16. */
  17. #include <asm-offsets.h>
  18. #include <config.h>
  19. /*
  20. *************************************************************************
  21. *
  22. * Startup Code (reset vector)
  23. *
  24. * do important init only if we don't start from memory!
  25. * setup Memory and board specific bits prior to relocation.
  26. * relocate armboot to ram
  27. * setup stack
  28. *
  29. *************************************************************************
  30. */
  31. .globl reset
  32. reset:
  33. /*
  34. * set the cpu to SVC32 mode
  35. */
  36. mrs r0,cpsr
  37. bic r0,r0,#0x1f
  38. orr r0,r0,#0xd3
  39. msr cpsr,r0
  40. /*
  41. * we do sys-critical inits only at reboot,
  42. * not when booting from ram!
  43. */
  44. #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  45. bl cpu_init_crit
  46. #endif
  47. bl _main
  48. /*------------------------------------------------------------------------------*/
  49. .globl c_runtime_cpu_setup
  50. c_runtime_cpu_setup:
  51. mov pc, lr
  52. /*
  53. *************************************************************************
  54. *
  55. * CPU_init_critical registers
  56. *
  57. * setup important registers
  58. * setup memory timing
  59. *
  60. *************************************************************************
  61. */
  62. #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  63. cpu_init_crit:
  64. /*
  65. * flush v4 I/D caches
  66. */
  67. mov r0, #0
  68. mcr p15, 0, r0, c7, c5, 0 /* flush v4 I-cache */
  69. mcr p15, 0, r0, c7, c6, 0 /* flush v4 D-cache */
  70. /*
  71. * disable MMU stuff and caches
  72. */
  73. mrc p15, 0, r0, c1, c0, 0
  74. bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */
  75. bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */
  76. orr r0, r0, #0x00000002 /* set bit 1 (A) Align */
  77. orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
  78. mcr p15, 0, r0, c1, c0, 0
  79. #ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
  80. /*
  81. * Go setup Memory and board specific bits prior to relocation.
  82. */
  83. mov ip, lr /* perserve link reg across call */
  84. bl lowlevel_init /* go setup memory */
  85. mov lr, ip /* restore link */
  86. #endif
  87. mov pc, lr /* back to my caller */
  88. #endif