Test/board-support/u-boot-2017.01+gitAUTOINC+340fb36f04-g340fb36f04/DIFF_20180314

diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
index 226eda5..3a0d1bf 100644
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c
@@ -123,10 +123,16 @@ static const struct emif_regs ddr2_evm_emif_reg_data = {
 };
 
 static const struct ddr_data ddr3_data = {
-	.datardsratio0 = MT41J128MJT125_RD_DQS,
+	/*+++ vern,20161126, for 512 DDR+++*/
+	/*.datardsratio0 = MT41J128MJT125_RD_DQS,
 	.datawdsratio0 = MT41J128MJT125_WR_DQS,
 	.datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE,
-	.datawrsratio0 = MT41J128MJT125_PHY_WR_DATA,
+	.datawrsratio0 = MT41J128MJT125_PHY_WR_DATA,*/
+	.datardsratio0 = MT41K256M16HA125E_RD_DQS,
+	.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
+	.datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
+	.datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
+		/*--- vern,20161126, for 512 DDR---*/	
 };
 
 static const struct ddr_data ddr3_beagleblack_data = {
@@ -137,10 +143,16 @@ static const struct ddr_data ddr3_beagleblack_data = {
 };
 
 static const struct ddr_data ddr3_evm_data = {
-	.datardsratio0 = MT41J512M8RH125_RD_DQS,
+	/*+++ vern,20161126, for 512 DDR+++*/
+/*	.datardsratio0 = MT41J512M8RH125_RD_DQS,
 	.datawdsratio0 = MT41J512M8RH125_WR_DQS,
 	.datafwsratio0 = MT41J512M8RH125_PHY_FIFO_WE,
-	.datawrsratio0 = MT41J512M8RH125_PHY_WR_DATA,
+	.datawrsratio0 = MT41J512M8RH125_PHY_WR_DATA,*/
+	.datardsratio0 = MT41K256M16HA125E_RD_DQS,
+	.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
+	.datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
+	.datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
+	/*--- vern,20161126, for 512 DDR---*/	
 };
 
 static const struct ddr_data ddr3_icev2_data = {
@@ -151,14 +163,24 @@ static const struct ddr_data ddr3_icev2_data = {
 };
 
 static const struct cmd_control ddr3_cmd_ctrl_data = {
-	.cmd0csratio = MT41J128MJT125_RATIO,
+	/*+++ vern,20161126, for 512 DDR+++*/
+	/*.cmd0csratio = MT41J128MJT125_RATIO,
 	.cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT,
 
 	.cmd1csratio = MT41J128MJT125_RATIO,
 	.cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT,
 
 	.cmd2csratio = MT41J128MJT125_RATIO,
-	.cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT,
+	.cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT,*/
+	.cmd0csratio = MT41K256M16HA125E_RATIO,
+	.cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+
+	.cmd1csratio = MT41K256M16HA125E_RATIO,
+	.cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+
+	.cmd2csratio = MT41K256M16HA125E_RATIO,
+	.cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+	/*--- vern,20161126, for 512 DDR---*/	
 };
 
 static const struct cmd_control ddr3_beagleblack_cmd_ctrl_data = {
@@ -173,14 +195,24 @@ static const struct cmd_control ddr3_beagleblack_cmd_ctrl_data = {
 };
 
 static const struct cmd_control ddr3_evm_cmd_ctrl_data = {
-	.cmd0csratio = MT41J512M8RH125_RATIO,
+	/*+++ vern,20161126, for 512 DDR+++*/
+	/*.cmd0csratio = MT41J512M8RH125_RATIO,
 	.cmd0iclkout = MT41J512M8RH125_INVERT_CLKOUT,
 
 	.cmd1csratio = MT41J512M8RH125_RATIO,
 	.cmd1iclkout = MT41J512M8RH125_INVERT_CLKOUT,
 
 	.cmd2csratio = MT41J512M8RH125_RATIO,
-	.cmd2iclkout = MT41J512M8RH125_INVERT_CLKOUT,
+	.cmd2iclkout = MT41J512M8RH125_INVERT_CLKOUT,*/
+	.cmd0csratio = MT41K256M16HA125E_RATIO,
+	.cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+
+	.cmd1csratio = MT41K256M16HA125E_RATIO,
+	.cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+
+	.cmd2csratio = MT41K256M16HA125E_RATIO,
+	.cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+		/*--- vern,20161126, for 512 DDR---*/
 };
 
 static const struct cmd_control ddr3_icev2_cmd_ctrl_data = {
@@ -195,14 +227,23 @@ static const struct cmd_control ddr3_icev2_cmd_ctrl_data = {
 };
 
 static struct emif_regs ddr3_emif_reg_data = {
-	.sdram_config = MT41J128MJT125_EMIF_SDCFG,
+	/*+++ vern,20161126, for 512 DDR+++*/
+	/*.sdram_config = MT41J128MJT125_EMIF_SDCFG,
 	.ref_ctrl = MT41J128MJT125_EMIF_SDREF,
 	.sdram_tim1 = MT41J128MJT125_EMIF_TIM1,
 	.sdram_tim2 = MT41J128MJT125_EMIF_TIM2,
 	.sdram_tim3 = MT41J128MJT125_EMIF_TIM3,
 	.zq_config = MT41J128MJT125_ZQ_CFG,
 	.emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY |
-				PHY_EN_DYN_PWRDN,
+				PHY_EN_DYN_PWRDN,*/
+	.sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
+	.ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
+	.sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
+	.sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
+	.sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
+	.zq_config = MT41K256M16HA125E_ZQ_CFG,
+	.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,		
+		/*--- vern,20161126, for 512 DDR---*/	
 };
 
 static struct emif_regs ddr3_beagleblack_emif_reg_data = {
@@ -217,15 +258,23 @@ static struct emif_regs ddr3_beagleblack_emif_reg_data = {
 };
 
 static struct emif_regs ddr3_evm_emif_reg_data = {
-	.sdram_config = MT41J512M8RH125_EMIF_SDCFG,
+	/*+++ vern,20161126, for 512 DDR+++*/
+	/*.sdram_config = MT41J512M8RH125_EMIF_SDCFG,
 	.ref_ctrl = MT41J512M8RH125_EMIF_SDREF,
 	.sdram_tim1 = MT41J512M8RH125_EMIF_TIM1,
 	.sdram_tim2 = MT41J512M8RH125_EMIF_TIM2,
 	.sdram_tim3 = MT41J512M8RH125_EMIF_TIM3,
-	.ocp_config = EMIF_OCP_CONFIG_AM335X_EVM,
 	.zq_config = MT41J512M8RH125_ZQ_CFG,
 	.emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY |
-				PHY_EN_DYN_PWRDN,
+				PHY_EN_DYN_PWRDN,*/
+	.sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
+	.ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
+	.sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
+	.sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
+	.sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
+	.zq_config = MT41K256M16HA125E_ZQ_CFG,
+	.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,		
+	/*--- vern,20161126, for 512 DDR---*/	
 };
 
 static struct emif_regs ddr3_icev2_emif_reg_data = {
@@ -268,7 +317,12 @@ const struct dpll_params *get_dpll_ddr_params(void)
 	else if (board_is_evm_15_or_later())
 		return &dpll_ddr3_303MHz[ind];
 	else
-		return &dpll_ddr2_266MHz[ind];
+	{
+		/*+++ vern,20161126, for 512 DDR+++*/
+		return &dpll_ddr3_303MHz[ind];
+		//return &dpll_ddr2_266MHz[ind];
+		/*--- vern,20161126, for 512 DDR ---*/
+	}
 }
 
 static u8 bone_not_connected_to_ac_power(void)
@@ -491,11 +545,18 @@ void set_mux_conf_regs(void)
 }
 
 const struct ctrl_ioregs ioregs_evmsk = {
-	.cm0ioctl		= MT41J128MJT125_IOCTRL_VALUE,
+	/*+++ vern,20161126, for 512 DDR+++*/
+	/*.cm0ioctl		= MT41J128MJT125_IOCTRL_VALUE,
 	.cm1ioctl		= MT41J128MJT125_IOCTRL_VALUE,
 	.cm2ioctl		= MT41J128MJT125_IOCTRL_VALUE,
 	.dt0ioctl		= MT41J128MJT125_IOCTRL_VALUE,
-	.dt1ioctl		= MT41J128MJT125_IOCTRL_VALUE,
+	.dt1ioctl		= MT41J128MJT125_IOCTRL_VALUE,*/
+	.cm0ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+	.cm1ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+	.cm2ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+	.dt0ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+	.dt1ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+	/*--- vern,20161126, for 512 DDR---*/
 };
 
 const struct ctrl_ioregs ioregs_bonelt = {
@@ -507,19 +568,33 @@ const struct ctrl_ioregs ioregs_bonelt = {
 };
 
 const struct ctrl_ioregs ioregs_evm15 = {
-	.cm0ioctl		= MT41J512M8RH125_IOCTRL_VALUE,
+	/*+++ vern,20161126, for 512 DDR+++*/
+	/*.cm0ioctl		= MT41J512M8RH125_IOCTRL_VALUE,
 	.cm1ioctl		= MT41J512M8RH125_IOCTRL_VALUE,
 	.cm2ioctl		= MT41J512M8RH125_IOCTRL_VALUE,
 	.dt0ioctl		= MT41J512M8RH125_IOCTRL_VALUE,
-	.dt1ioctl		= MT41J512M8RH125_IOCTRL_VALUE,
+	.dt1ioctl		= MT41J512M8RH125_IOCTRL_VALUE,*/
+	.cm0ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+	.cm1ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+	.cm2ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+	.dt0ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+	.dt1ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+	/*--- vern,20161126, for 512 DDR---*/
 };
 
 const struct ctrl_ioregs ioregs = {
-	.cm0ioctl		= MT47H128M16RT25E_IOCTRL_VALUE,
+	/*+++ vern,20161126, for 512 DDR+++*/
+	/*.cm0ioctl		= MT47H128M16RT25E_IOCTRL_VALUE,
 	.cm1ioctl		= MT47H128M16RT25E_IOCTRL_VALUE,
 	.cm2ioctl		= MT47H128M16RT25E_IOCTRL_VALUE,
 	.dt0ioctl		= MT47H128M16RT25E_IOCTRL_VALUE,
-	.dt1ioctl		= MT47H128M16RT25E_IOCTRL_VALUE,
+	.dt1ioctl		= MT47H128M16RT25E_IOCTRL_VALUE,*/
+	.cm0ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+	.cm1ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+	.cm2ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+	.dt0ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+	.dt1ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+	/*--- vern,20161126, for 512 DDR---*/
 };
 
 void sdram_init(void)
@@ -553,12 +628,19 @@ void sdram_init(void)
 		config_ddr(400, &ioregs_evmsk, &ddr3_icev2_data,
 			   &ddr3_icev2_cmd_ctrl_data, &ddr3_icev2_emif_reg_data,
 			   0);
+	/*+++ vern,20161126, for 512 DDR+++*/
+	/*
 	else if (board_is_gp_evm())
 		config_ddr(266, &ioregs, &ddr2_data,
 			   &ddr2_cmd_ctrl_data, &ddr2_evm_emif_reg_data, 0);
 	else
 		config_ddr(266, &ioregs, &ddr2_data,
 			   &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
+	*/
+	else
+		config_ddr(303, &ioregs_evm15, &ddr3_evm_data,
+			   &ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0);	
+	/*--- vern,20161126, for 512 DDR ---*/
 }
 #endif
 
diff --git a/board/ti/am335x/mux.c b/board/ti/am335x/mux.c
index ad85b3a..972a5ed 100644
--- a/board/ti/am335x/mux.c
+++ b/board/ti/am335x/mux.c
@@ -66,7 +66,10 @@ static struct module_pin_mux mmc0_pin_mux[] = {
 	{OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_CLK */
 	{OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_CMD */
 	{OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)},		/* MMC0_WP */
-	{OFFSET(spi0_cs1), (MODE(7) | RXACTIVE | PULLUP_EN)},	/* GPIO0_6 */
+	/*+++ vern,20161126, for mmc0 +++*/
+	//{OFFSET(spi0_cs1), (MODE(7) | RXACTIVE | PULLUP_EN)},	/* GPIO0_6 */
+	{OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)},	/* MMC0_CD */
+	/*--- vern,20161126, for mmc0 ---*/
 	{-1},
 };
 
@@ -201,7 +204,10 @@ static struct module_pin_mux nand_pin_mux[] = {
 	{OFFSET(gpmc_ad5),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD5  */
 	{OFFSET(gpmc_ad6),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD6  */
 	{OFFSET(gpmc_ad7),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD7  */
-#ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT
+/*+++ vern,20161126, for rgmii2 +++*/			
+//#ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT
+#if 0
+/*--- vern,20161126, for rgmii2 ---*/	
 	{OFFSET(gpmc_ad8),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD8  */
 	{OFFSET(gpmc_ad9),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD9  */
 	{OFFSET(gpmc_ad10),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD10 */
@@ -357,6 +363,9 @@ void enable_board_pin_mux(void)
 		unsigned short profile = detect_daughter_board_profile();
 		configure_module_pin_mux(rgmii1_pin_mux);
 		configure_module_pin_mux(mmc0_pin_mux);
+		configure_module_pin_mux(nand_pin_mux);/*+++ vern,20161126, for 2G NAND ---*/
+		/*+++ vern,20161126, for rgmii2 +++*/		
+		#if 0	
 		/* In profile #2 i2c1 and spi0 conflict. */
 		if (profile & ~PROFILE_2)
 			configure_module_pin_mux(i2c1_pin_mux);
@@ -369,6 +378,8 @@ void enable_board_pin_mux(void)
 			configure_module_pin_mux(mmc1_pin_mux);
 			configure_module_pin_mux(spi0_pin_mux);
 		}
+		#endif		
+		/*--- vern,20161126, for rgmii2 ---*/
 	} else if (board_is_idk()) {
 		/* Industrial Motor Control (IDK) */
 		configure_module_pin_mux(mii1_pin_mux);
diff --git a/board/ti/common/board_detect.c b/board/ti/common/board_detect.c
index 6414958..ed4a9b2 100644
--- a/board/ti/common/board_detect.c
+++ b/board/ti/common/board_detect.c
@@ -180,6 +180,8 @@ int __maybe_unused ti_i2c_eeprom_am_get(int bus_addr, int dev_addr)
 #endif
 
 	/* Initialize with a known bad marker for i2c fails.. */
+	/*+++ vern,20161126, No EEPROM +++*/
+	/*
 	ep->header = TI_DEAD_EEPROM_MAGIC;
 	ep->name[0] = 0x0;
 	ep->version[0] = 0x0;
@@ -194,8 +196,9 @@ int __maybe_unused ti_i2c_eeprom_am_get(int bus_addr, int dev_addr)
 	ep->header = am_ep.header;
 	strlcpy(ep->name, am_ep.name, TI_EEPROM_HDR_NAME_LEN + 1);
 	ti_eeprom_string_cleanup(ep->name);
-
+	*/
 	/* BeagleBone Green '1' eeprom, board_rev: 0x1a 0x00 0x00 0x00 */
+	/*
 	if (am_ep.version[0] == 0x1a && am_ep.version[1] == 0x00 &&
 	    am_ep.version[2] == 0x00 && am_ep.version[3] == 0x00)
 		strlcpy(ep->version, "BBG1", TI_EEPROM_HDR_REV_LEN + 1);
@@ -209,6 +212,12 @@ int __maybe_unused ti_i2c_eeprom_am_get(int bus_addr, int dev_addr)
 
 	memcpy(ep->mac_addr, am_ep.mac_addr,
 	       TI_EEPROM_HDR_NO_OF_MAC_ADDR * TI_EEPROM_HDR_ETH_ALEN);
+	*/
+	memset(ep, 0, sizeof(struct ti_common_eeprom));
+	ep->header = TI_EEPROM_HEADER_MAGIC;
+	strlcpy(ep->name, "A33515BB", TI_EEPROM_HDR_NAME_LEN + 1);
+	strlcpy(ep->version, "1.0", TI_EEPROM_HDR_REV_LEN + 1);
+	/*--- vern,20161126,  No EEPROM ---*/
 
 	return 0;
 }
diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
index bc1f2b2..4a65966 100644
--- a/include/configs/am335x_evm.h
+++ b/include/configs/am335x_evm.h
@@ -37,14 +37,28 @@
 #define CONFIG_SYS_LDSCRIPT		"board/ti/am335x/u-boot.lds"
 
 /* Always 128 KiB env size */
-#define CONFIG_ENV_SIZE			(128 << 10)
+#define CONFIG_ENV_SIZE			(512 << 10)//(128 << 10)/*++++ vern,set up environment,20161127 ---*/
 
 /* Enhance our eMMC support / experience. */
 #define CONFIG_CMD_GPT
 #define CONFIG_EFI_PARTITION
 
 #ifdef CONFIG_NAND
+/*++++ vern,set up environment,20161127 +++*/
+#define CONFIG_ENV_IS_IN_NAND		1/*++++ vern,set up environment,20161127 ---*/
 #define NANDARGS \
+	"bootargs=console=ttyS0,115200n8 mem=512M root=/dev/ram0 rw initrd=0x81000000,64M ramdisk_size=67108864\0" \
+	"ipaddr=192.168.1.10\0" \
+	"serverip=192.168.1.1\0" \
+	"gatewayip=192.168.1.1\0" \
+	"netmask=255.255.255.0\0" \
+	"nandboot=" \
+		"nand read 0x80F80000 0x00200000 0x00080000;" \
+		"nand read 0x80200000 0x00280000 0x00A00000;" \
+		"nand read 0x81000000 0x00C80000 0x00A00000;" \
+		"bootz 0x80200000 - 0x80F80000\0"
+
+/*#define NANDARGS \
 	"mtdids=" MTDIDS_DEFAULT "\0" \
 	"mtdparts=" MTDPARTS_DEFAULT "\0" \
 	"nandargs=setenv bootargs console=${console} " \
@@ -58,6 +72,8 @@
 		"nand read ${fdtaddr} NAND.u-boot-spl-os; " \
 		"nand read ${loadaddr} NAND.kernel; " \
 		"bootz ${loadaddr} - ${fdtaddr}\0"
+*/
+/*--- vern,set up environment,20161127 ---*/
 #else
 #define NANDARGS ""
 #endif
@@ -89,6 +105,9 @@
 	func(PXE, pxe, na) \
 	func(DHCP, dhcp, na)
 
+/*++++ vern,set up environment,20161127 +++*/
+#define CONFIG_BOOTCOMMAND	"run nandboot;" 
+/*
 #define CONFIG_BOOTCOMMAND \
 	"if test ${boot_fit} -eq 1; then "	\
 		"run update_to_fit;"	\
@@ -97,10 +116,15 @@
 	"run init_console; " \
 	"run envboot; " \
 	"run distro_bootcmd"
+*/
+/*--- vern,set up environment,20161127 ---*/
 
 #include <config_distro_bootcmd.h>
 
 #ifndef CONFIG_SPL_BUILD
+/*++++ vern,set up environment,20161127 +++*/
+#define CONFIG_EXTRA_ENV_SETTINGS	NANDARGS 
+/*
 #include <environment/ti/dfu.h>
 #include <environment/ti/mmc.h>
 
@@ -166,6 +190,8 @@
 	NETARGS \
 	DFUARGS \
 	BOOTENV
+*/	
+/*--- vern,set up environment,20161127 ---*/
 #endif
 
 /* NS16550 Configuration */
@@ -203,28 +229,57 @@
 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
 #define CONFIG_SYS_NAND_PAGE_COUNT	(CONFIG_SYS_NAND_BLOCK_SIZE / \
 					 CONFIG_SYS_NAND_PAGE_SIZE)
-#define CONFIG_SYS_NAND_PAGE_SIZE	2048
-#define CONFIG_SYS_NAND_OOBSIZE		64
-#define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)
+#define CONFIG_SYS_NAND_PAGE_SIZE	4096//2048 /*++++ vern,NAND,20161127 ---*/
+#define CONFIG_SYS_NAND_OOBSIZE		224//64 /*++++ vern,NAND,20161127 ---*/
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(64*4096)//(128*1024)/*++++ vern,NAND,20161127 ---*/
 /* NAND: driver related configs */
 #define CONFIG_NAND_OMAP_GPMC
 #define CONFIG_NAND_OMAP_GPMC_PREFETCH
 #define CONFIG_NAND_OMAP_ELM
 #define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
-#define CONFIG_SYS_NAND_ECCPOS		{ 2, 3, 4, 5, 6, 7, 8, 9, \
+ /*++++ vern,NAND,20161127 +++*/
+/*每512 Bytes 的page size需加上14 Bytes
+  所以4096 page size 需加上 (4096/512)*14=112 Bytes
+*/
+
+#define CONFIG_SYS_NAND_ECCPOS	   {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
+									16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, \
+									28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, \
+									40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, \
+									52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
+									64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, \
+									76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, \
+									88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, \
+									100, 101, 102, 103, 104, 105, 106, 107, 108, 109, \
+									110, 111, 112, 113 }
+								
+
+/*#define CONFIG_SYS_NAND_ECCPOS		{ 2, 3, 4, 5, 6, 7, 8, 9, \
 					 10, 11, 12, 13, 14, 15, 16, 17, \
 					 18, 19, 20, 21, 22, 23, 24, 25, \
 					 26, 27, 28, 29, 30, 31, 32, 33, \
 					 34, 35, 36, 37, 38, 39, 40, 41, \
 					 42, 43, 44, 45, 46, 47, 48, 49, \
 					 50, 51, 52, 53, 54, 55, 56, 57, }
+*/					 
 
-#define CONFIG_SYS_NAND_ECCSIZE		512
-#define CONFIG_SYS_NAND_ECCBYTES	14
+#define CONFIG_SYS_NAND_ECCSIZE		512 /*每512 Bytes 的page size需加上14 Bytes*/
+#define CONFIG_SYS_NAND_ECCBYTES	14	/*每512 Bytes 的page size需加上14 Bytes*/
+ /*--- vern,NAND,20161127 ---*/
 #define CONFIG_SYS_NAND_ONFI_DETECTION
 #define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_BCH8_CODE_HW
 #define MTDIDS_DEFAULT			"nand0=nand.0"
-#define MTDPARTS_DEFAULT		"mtdparts=nand.0:" \
+/*++++ vern,set up environment,20161127 +++*/
+/*#define MTDPARTS_DEFAULT		"mtdparts=nand.0:" \
+								"512k(NAND.SPL)," \
+								"1m(NAND.u-boot)," \
+								"512k(NAND.u-boot-env)," \
+								"512k(NAND.u-boot-spl-os)," \
+								"7.5m(NAND.kernel)," \
+								"-(NAND.file-system)"
+					
+*/					
+/*#define MTDPARTS_DEFAULT		"mtdparts=nand.0:" \
 					"128k(NAND.SPL)," \
 					"128k(NAND.SPL.backup1)," \
 					"128k(NAND.SPL.backup2)," \
@@ -235,14 +290,23 @@
 					"128k(NAND.u-boot-env.backup1)," \
 					"8m(NAND.kernel)," \
 					"-(NAND.file-system)"
-#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x000c0000
+*/
+
+/*#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x000c0000*/
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x00080000
+/*--- vern,set up environment,20161127 ---*/
+
 /* NAND: SPL related configs */
 #ifdef CONFIG_SPL_NAND_SUPPORT
 #define CONFIG_SPL_NAND_AM33XX_BCH
 #endif
 #ifdef CONFIG_SPL_OS_BOOT
-#define CONFIG_CMD_SPL_NAND_OFS	0x00080000 /* os parameters */
-#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS	0x00200000 /* kernel offset */
+/*++++ vern,set up environment,20161127 +++*/
+/*#define CONFIG_CMD_SPL_NAND_OFS	0x00080000 *//* os parameters */
+#define CONFIG_CMD_SPL_NAND_OFS	0x00200000 /* os parameters */
+/*#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS	0x00200000 *//* kernel offset */
+#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS	0x00280000 /* kernel offset */
+/*--- vern,set up environment,20161127 ---*/
 #define CONFIG_CMD_SPL_WRITE_SIZE	0x2000
 #endif
 #endif /* !CONFIG_NAND */
@@ -359,12 +423,15 @@
 					"128k(u-boot-env2)," \
 					"4m(kernel),-(rootfs)"
 #elif defined(CONFIG_ENV_IS_IN_NAND)
-#define CONFIG_ENV_OFFSET		0x001c0000
-#define CONFIG_ENV_OFFSET_REDUND	0x001e0000
+/*++++ vern,set up environment,20161127 +++*/
+/*#define CONFIG_ENV_OFFSET		0x001c0000*/
+#define CONFIG_ENV_OFFSET		0x00180000
+/*#define CONFIG_ENV_OFFSET_REDUND	0x001e0000*/
+/*--- vern,set up environment,20161127 ---*/
 #define CONFIG_SYS_ENV_SECT_SIZE	CONFIG_SYS_NAND_BLOCK_SIZE
 #elif !defined(CONFIG_ENV_IS_NOWHERE)
 /* Not NAND, SPI, NOR or eMMC env, so put ENV in a file on FAT */
-#define CONFIG_ENV_IS_IN_FAT
+//#define CONFIG_ENV_IS_IN_FAT	/*++++ vern,set up environment,20161127 ---*/
 #define FAT_ENV_INTERFACE		"mmc"
 #define FAT_ENV_DEVICE_AND_PART		"0:1"
 #define FAT_ENV_FILE			"uboot.env"