qe.h 27 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807
  1. /*
  2. * Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved.
  3. *
  4. * Authors: Shlomi Gridish <gridish@freescale.com>
  5. * Li Yang <leoli@freescale.com>
  6. *
  7. * Description:
  8. * QUICC Engine (QE) external definitions and structure.
  9. *
  10. * This program is free software; you can redistribute it and/or modify it
  11. * under the terms of the GNU General Public License as published by the
  12. * Free Software Foundation; either version 2 of the License, or (at your
  13. * option) any later version.
  14. */
  15. #ifndef _ASM_POWERPC_QE_H
  16. #define _ASM_POWERPC_QE_H
  17. #ifdef __KERNEL__
  18. #include <linux/compiler.h>
  19. #include <linux/genalloc.h>
  20. #include <linux/spinlock.h>
  21. #include <linux/errno.h>
  22. #include <linux/err.h>
  23. #include <asm/cpm.h>
  24. #include <soc/fsl/qe/immap_qe.h>
  25. #include <linux/of.h>
  26. #include <linux/of_address.h>
  27. #include <linux/types.h>
  28. #define QE_NUM_OF_SNUM 256 /* There are 256 serial number in QE */
  29. #define QE_NUM_OF_BRGS 16
  30. #define QE_NUM_OF_PORTS 1024
  31. /* Memory partitions
  32. */
  33. #define MEM_PART_SYSTEM 0
  34. #define MEM_PART_SECONDARY 1
  35. #define MEM_PART_MURAM 2
  36. /* Clocks and BRGs */
  37. enum qe_clock {
  38. QE_CLK_NONE = 0,
  39. QE_BRG1, /* Baud Rate Generator 1 */
  40. QE_BRG2, /* Baud Rate Generator 2 */
  41. QE_BRG3, /* Baud Rate Generator 3 */
  42. QE_BRG4, /* Baud Rate Generator 4 */
  43. QE_BRG5, /* Baud Rate Generator 5 */
  44. QE_BRG6, /* Baud Rate Generator 6 */
  45. QE_BRG7, /* Baud Rate Generator 7 */
  46. QE_BRG8, /* Baud Rate Generator 8 */
  47. QE_BRG9, /* Baud Rate Generator 9 */
  48. QE_BRG10, /* Baud Rate Generator 10 */
  49. QE_BRG11, /* Baud Rate Generator 11 */
  50. QE_BRG12, /* Baud Rate Generator 12 */
  51. QE_BRG13, /* Baud Rate Generator 13 */
  52. QE_BRG14, /* Baud Rate Generator 14 */
  53. QE_BRG15, /* Baud Rate Generator 15 */
  54. QE_BRG16, /* Baud Rate Generator 16 */
  55. QE_CLK1, /* Clock 1 */
  56. QE_CLK2, /* Clock 2 */
  57. QE_CLK3, /* Clock 3 */
  58. QE_CLK4, /* Clock 4 */
  59. QE_CLK5, /* Clock 5 */
  60. QE_CLK6, /* Clock 6 */
  61. QE_CLK7, /* Clock 7 */
  62. QE_CLK8, /* Clock 8 */
  63. QE_CLK9, /* Clock 9 */
  64. QE_CLK10, /* Clock 10 */
  65. QE_CLK11, /* Clock 11 */
  66. QE_CLK12, /* Clock 12 */
  67. QE_CLK13, /* Clock 13 */
  68. QE_CLK14, /* Clock 14 */
  69. QE_CLK15, /* Clock 15 */
  70. QE_CLK16, /* Clock 16 */
  71. QE_CLK17, /* Clock 17 */
  72. QE_CLK18, /* Clock 18 */
  73. QE_CLK19, /* Clock 19 */
  74. QE_CLK20, /* Clock 20 */
  75. QE_CLK21, /* Clock 21 */
  76. QE_CLK22, /* Clock 22 */
  77. QE_CLK23, /* Clock 23 */
  78. QE_CLK24, /* Clock 24 */
  79. QE_RSYNC_PIN, /* RSYNC from pin */
  80. QE_TSYNC_PIN, /* TSYNC from pin */
  81. QE_CLK_DUMMY
  82. };
  83. static inline bool qe_clock_is_brg(enum qe_clock clk)
  84. {
  85. return clk >= QE_BRG1 && clk <= QE_BRG16;
  86. }
  87. extern spinlock_t cmxgcr_lock;
  88. /* Export QE common operations */
  89. #ifdef CONFIG_QUICC_ENGINE
  90. extern void qe_reset(void);
  91. #else
  92. static inline void qe_reset(void) {}
  93. #endif
  94. int cpm_muram_init(void);
  95. #if defined(CONFIG_CPM) || defined(CONFIG_QUICC_ENGINE)
  96. unsigned long cpm_muram_alloc(unsigned long size, unsigned long align);
  97. int cpm_muram_free(unsigned long offset);
  98. unsigned long cpm_muram_alloc_fixed(unsigned long offset, unsigned long size);
  99. void __iomem *cpm_muram_addr(unsigned long offset);
  100. unsigned long cpm_muram_offset(void __iomem *addr);
  101. dma_addr_t cpm_muram_dma(void __iomem *addr);
  102. #else
  103. static inline unsigned long cpm_muram_alloc(unsigned long size,
  104. unsigned long align)
  105. {
  106. return -ENOSYS;
  107. }
  108. static inline int cpm_muram_free(unsigned long offset)
  109. {
  110. return -ENOSYS;
  111. }
  112. static inline unsigned long cpm_muram_alloc_fixed(unsigned long offset,
  113. unsigned long size)
  114. {
  115. return -ENOSYS;
  116. }
  117. static inline void __iomem *cpm_muram_addr(unsigned long offset)
  118. {
  119. return NULL;
  120. }
  121. static inline unsigned long cpm_muram_offset(void __iomem *addr)
  122. {
  123. return -ENOSYS;
  124. }
  125. static inline dma_addr_t cpm_muram_dma(void __iomem *addr)
  126. {
  127. return 0;
  128. }
  129. #endif /* defined(CONFIG_CPM) || defined(CONFIG_QUICC_ENGINE) */
  130. /* QE PIO */
  131. #define QE_PIO_PINS 32
  132. struct qe_pio_regs {
  133. __be32 cpodr; /* Open drain register */
  134. __be32 cpdata; /* Data register */
  135. __be32 cpdir1; /* Direction register */
  136. __be32 cpdir2; /* Direction register */
  137. __be32 cppar1; /* Pin assignment register */
  138. __be32 cppar2; /* Pin assignment register */
  139. #ifdef CONFIG_PPC_85xx
  140. u8 pad[8];
  141. #endif
  142. };
  143. #define QE_PIO_DIR_IN 2
  144. #define QE_PIO_DIR_OUT 1
  145. extern void __par_io_config_pin(struct qe_pio_regs __iomem *par_io, u8 pin,
  146. int dir, int open_drain, int assignment,
  147. int has_irq);
  148. #ifdef CONFIG_QUICC_ENGINE
  149. extern int par_io_init(struct device_node *np);
  150. extern int par_io_of_config(struct device_node *np);
  151. extern int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain,
  152. int assignment, int has_irq);
  153. extern int par_io_data_set(u8 port, u8 pin, u8 val);
  154. #else
  155. static inline int par_io_init(struct device_node *np) { return -ENOSYS; }
  156. static inline int par_io_of_config(struct device_node *np) { return -ENOSYS; }
  157. static inline int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain,
  158. int assignment, int has_irq) { return -ENOSYS; }
  159. static inline int par_io_data_set(u8 port, u8 pin, u8 val) { return -ENOSYS; }
  160. #endif /* CONFIG_QUICC_ENGINE */
  161. /*
  162. * Pin multiplexing functions.
  163. */
  164. struct qe_pin;
  165. #ifdef CONFIG_QE_GPIO
  166. extern struct qe_pin *qe_pin_request(struct device_node *np, int index);
  167. extern void qe_pin_free(struct qe_pin *qe_pin);
  168. extern void qe_pin_set_gpio(struct qe_pin *qe_pin);
  169. extern void qe_pin_set_dedicated(struct qe_pin *pin);
  170. #else
  171. static inline struct qe_pin *qe_pin_request(struct device_node *np, int index)
  172. {
  173. return ERR_PTR(-ENOSYS);
  174. }
  175. static inline void qe_pin_free(struct qe_pin *qe_pin) {}
  176. static inline void qe_pin_set_gpio(struct qe_pin *qe_pin) {}
  177. static inline void qe_pin_set_dedicated(struct qe_pin *pin) {}
  178. #endif /* CONFIG_QE_GPIO */
  179. #ifdef CONFIG_QUICC_ENGINE
  180. int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input);
  181. #else
  182. static inline int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol,
  183. u32 cmd_input)
  184. {
  185. return -ENOSYS;
  186. }
  187. #endif /* CONFIG_QUICC_ENGINE */
  188. /* QE internal API */
  189. enum qe_clock qe_clock_source(const char *source);
  190. unsigned int qe_get_brg_clk(void);
  191. int qe_setbrg(enum qe_clock brg, unsigned int rate, unsigned int multiplier);
  192. int qe_get_snum(void);
  193. void qe_put_snum(u8 snum);
  194. unsigned int qe_get_num_of_risc(void);
  195. unsigned int qe_get_num_of_snums(void);
  196. static inline int qe_alive_during_sleep(void)
  197. {
  198. /*
  199. * MPC8568E reference manual says:
  200. *
  201. * "...power down sequence waits for all I/O interfaces to become idle.
  202. * In some applications this may happen eventually without actively
  203. * shutting down interfaces, but most likely, software will have to
  204. * take steps to shut down the eTSEC, QUICC Engine Block, and PCI
  205. * interfaces before issuing the command (either the write to the core
  206. * MSR[WE] as described above or writing to POWMGTCSR) to put the
  207. * device into sleep state."
  208. *
  209. * MPC8569E reference manual has a similar paragraph.
  210. */
  211. #ifdef CONFIG_PPC_85xx
  212. return 0;
  213. #else
  214. return 1;
  215. #endif
  216. }
  217. /* we actually use cpm_muram implementation, define this for convenience */
  218. #define qe_muram_init cpm_muram_init
  219. #define qe_muram_alloc cpm_muram_alloc
  220. #define qe_muram_alloc_fixed cpm_muram_alloc_fixed
  221. #define qe_muram_free cpm_muram_free
  222. #define qe_muram_addr cpm_muram_addr
  223. #define qe_muram_offset cpm_muram_offset
  224. #define qe_setbits32(_addr, _v) iowrite32be(ioread32be(_addr) | (_v), (_addr))
  225. #define qe_clrbits32(_addr, _v) iowrite32be(ioread32be(_addr) & ~(_v), (_addr))
  226. #define qe_setbits16(_addr, _v) iowrite16be(ioread16be(_addr) | (_v), (_addr))
  227. #define qe_clrbits16(_addr, _v) iowrite16be(ioread16be(_addr) & ~(_v), (_addr))
  228. #define qe_setbits8(_addr, _v) iowrite8(ioread8(_addr) | (_v), (_addr))
  229. #define qe_clrbits8(_addr, _v) iowrite8(ioread8(_addr) & ~(_v), (_addr))
  230. #define qe_clrsetbits32(addr, clear, set) \
  231. iowrite32be((ioread32be(addr) & ~(clear)) | (set), (addr))
  232. #define qe_clrsetbits16(addr, clear, set) \
  233. iowrite16be((ioread16be(addr) & ~(clear)) | (set), (addr))
  234. #define qe_clrsetbits8(addr, clear, set) \
  235. iowrite8((ioread8(addr) & ~(clear)) | (set), (addr))
  236. /* Structure that defines QE firmware binary files.
  237. *
  238. * See Documentation/powerpc/qe_firmware.txt for a description of these
  239. * fields.
  240. */
  241. struct qe_firmware {
  242. struct qe_header {
  243. __be32 length; /* Length of the entire structure, in bytes */
  244. u8 magic[3]; /* Set to { 'Q', 'E', 'F' } */
  245. u8 version; /* Version of this layout. First ver is '1' */
  246. } header;
  247. u8 id[62]; /* Null-terminated identifier string */
  248. u8 split; /* 0 = shared I-RAM, 1 = split I-RAM */
  249. u8 count; /* Number of microcode[] structures */
  250. struct {
  251. __be16 model; /* The SOC model */
  252. u8 major; /* The SOC revision major */
  253. u8 minor; /* The SOC revision minor */
  254. } __attribute__ ((packed)) soc;
  255. u8 padding[4]; /* Reserved, for alignment */
  256. __be64 extended_modes; /* Extended modes */
  257. __be32 vtraps[8]; /* Virtual trap addresses */
  258. u8 reserved[4]; /* Reserved, for future expansion */
  259. struct qe_microcode {
  260. u8 id[32]; /* Null-terminated identifier */
  261. __be32 traps[16]; /* Trap addresses, 0 == ignore */
  262. __be32 eccr; /* The value for the ECCR register */
  263. __be32 iram_offset; /* Offset into I-RAM for the code */
  264. __be32 count; /* Number of 32-bit words of the code */
  265. __be32 code_offset; /* Offset of the actual microcode */
  266. u8 major; /* The microcode version major */
  267. u8 minor; /* The microcode version minor */
  268. u8 revision; /* The microcode version revision */
  269. u8 padding; /* Reserved, for alignment */
  270. u8 reserved[4]; /* Reserved, for future expansion */
  271. } __attribute__ ((packed)) microcode[1];
  272. /* All microcode binaries should be located here */
  273. /* CRC32 should be located here, after the microcode binaries */
  274. } __attribute__ ((packed));
  275. struct qe_firmware_info {
  276. char id[64]; /* Firmware name */
  277. u32 vtraps[8]; /* Virtual trap addresses */
  278. u64 extended_modes; /* Extended modes */
  279. };
  280. #ifdef CONFIG_QUICC_ENGINE
  281. /* Upload a firmware to the QE */
  282. int qe_upload_firmware(const struct qe_firmware *firmware);
  283. #else
  284. static inline int qe_upload_firmware(const struct qe_firmware *firmware)
  285. {
  286. return -ENOSYS;
  287. }
  288. #endif /* CONFIG_QUICC_ENGINE */
  289. /* Obtain information on the uploaded firmware */
  290. struct qe_firmware_info *qe_get_firmware_info(void);
  291. /* QE USB */
  292. int qe_usb_clock_set(enum qe_clock clk, int rate);
  293. /* Buffer descriptors */
  294. struct qe_bd {
  295. __be16 status;
  296. __be16 length;
  297. __be32 buf;
  298. } __attribute__ ((packed));
  299. #define BD_STATUS_MASK 0xffff0000
  300. #define BD_LENGTH_MASK 0x0000ffff
  301. /* Alignment */
  302. #define QE_INTR_TABLE_ALIGN 16 /* ??? */
  303. #define QE_ALIGNMENT_OF_BD 8
  304. #define QE_ALIGNMENT_OF_PRAM 64
  305. /* RISC allocation */
  306. #define QE_RISC_ALLOCATION_RISC1 0x1 /* RISC 1 */
  307. #define QE_RISC_ALLOCATION_RISC2 0x2 /* RISC 2 */
  308. #define QE_RISC_ALLOCATION_RISC3 0x4 /* RISC 3 */
  309. #define QE_RISC_ALLOCATION_RISC4 0x8 /* RISC 4 */
  310. #define QE_RISC_ALLOCATION_RISC1_AND_RISC2 (QE_RISC_ALLOCATION_RISC1 | \
  311. QE_RISC_ALLOCATION_RISC2)
  312. #define QE_RISC_ALLOCATION_FOUR_RISCS (QE_RISC_ALLOCATION_RISC1 | \
  313. QE_RISC_ALLOCATION_RISC2 | \
  314. QE_RISC_ALLOCATION_RISC3 | \
  315. QE_RISC_ALLOCATION_RISC4)
  316. /* QE extended filtering Table Lookup Key Size */
  317. enum qe_fltr_tbl_lookup_key_size {
  318. QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES
  319. = 0x3f, /* LookupKey parsed by the Generate LookupKey
  320. CMD is truncated to 8 bytes */
  321. QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES
  322. = 0x5f, /* LookupKey parsed by the Generate LookupKey
  323. CMD is truncated to 16 bytes */
  324. };
  325. /* QE FLTR extended filtering Largest External Table Lookup Key Size */
  326. enum qe_fltr_largest_external_tbl_lookup_key_size {
  327. QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE
  328. = 0x0,/* not used */
  329. QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_8_BYTES
  330. = QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES, /* 8 bytes */
  331. QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_16_BYTES
  332. = QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES, /* 16 bytes */
  333. };
  334. /* structure representing QE parameter RAM */
  335. struct qe_timer_tables {
  336. u16 tm_base; /* QE timer table base adr */
  337. u16 tm_ptr; /* QE timer table pointer */
  338. u16 r_tmr; /* QE timer mode register */
  339. u16 r_tmv; /* QE timer valid register */
  340. u32 tm_cmd; /* QE timer cmd register */
  341. u32 tm_cnt; /* QE timer internal cnt */
  342. } __attribute__ ((packed));
  343. #define QE_FLTR_TAD_SIZE 8
  344. /* QE extended filtering Termination Action Descriptor (TAD) */
  345. struct qe_fltr_tad {
  346. u8 serialized[QE_FLTR_TAD_SIZE];
  347. } __attribute__ ((packed));
  348. /* Communication Direction */
  349. enum comm_dir {
  350. COMM_DIR_NONE = 0,
  351. COMM_DIR_RX = 1,
  352. COMM_DIR_TX = 2,
  353. COMM_DIR_RX_AND_TX = 3
  354. };
  355. /* QE CMXUCR Registers.
  356. * There are two UCCs represented in each of the four CMXUCR registers.
  357. * These values are for the UCC in the LSBs
  358. */
  359. #define QE_CMXUCR_MII_ENET_MNG 0x00007000
  360. #define QE_CMXUCR_MII_ENET_MNG_SHIFT 12
  361. #define QE_CMXUCR_GRANT 0x00008000
  362. #define QE_CMXUCR_TSA 0x00004000
  363. #define QE_CMXUCR_BKPT 0x00000100
  364. #define QE_CMXUCR_TX_CLK_SRC_MASK 0x0000000F
  365. /* QE CMXGCR Registers.
  366. */
  367. #define QE_CMXGCR_MII_ENET_MNG 0x00007000
  368. #define QE_CMXGCR_MII_ENET_MNG_SHIFT 12
  369. #define QE_CMXGCR_USBCS 0x0000000f
  370. #define QE_CMXGCR_USBCS_CLK3 0x1
  371. #define QE_CMXGCR_USBCS_CLK5 0x2
  372. #define QE_CMXGCR_USBCS_CLK7 0x3
  373. #define QE_CMXGCR_USBCS_CLK9 0x4
  374. #define QE_CMXGCR_USBCS_CLK13 0x5
  375. #define QE_CMXGCR_USBCS_CLK17 0x6
  376. #define QE_CMXGCR_USBCS_CLK19 0x7
  377. #define QE_CMXGCR_USBCS_CLK21 0x8
  378. #define QE_CMXGCR_USBCS_BRG9 0x9
  379. #define QE_CMXGCR_USBCS_BRG10 0xa
  380. /* QE CECR Commands.
  381. */
  382. #define QE_CR_FLG 0x00010000
  383. #define QE_RESET 0x80000000
  384. #define QE_INIT_TX_RX 0x00000000
  385. #define QE_INIT_RX 0x00000001
  386. #define QE_INIT_TX 0x00000002
  387. #define QE_ENTER_HUNT_MODE 0x00000003
  388. #define QE_STOP_TX 0x00000004
  389. #define QE_GRACEFUL_STOP_TX 0x00000005
  390. #define QE_RESTART_TX 0x00000006
  391. #define QE_CLOSE_RX_BD 0x00000007
  392. #define QE_SWITCH_COMMAND 0x00000007
  393. #define QE_SET_GROUP_ADDRESS 0x00000008
  394. #define QE_START_IDMA 0x00000009
  395. #define QE_MCC_STOP_RX 0x00000009
  396. #define QE_ATM_TRANSMIT 0x0000000a
  397. #define QE_HPAC_CLEAR_ALL 0x0000000b
  398. #define QE_GRACEFUL_STOP_RX 0x0000001a
  399. #define QE_RESTART_RX 0x0000001b
  400. #define QE_HPAC_SET_PRIORITY 0x0000010b
  401. #define QE_HPAC_STOP_TX 0x0000020b
  402. #define QE_HPAC_STOP_RX 0x0000030b
  403. #define QE_HPAC_GRACEFUL_STOP_TX 0x0000040b
  404. #define QE_HPAC_GRACEFUL_STOP_RX 0x0000050b
  405. #define QE_HPAC_START_TX 0x0000060b
  406. #define QE_HPAC_START_RX 0x0000070b
  407. #define QE_USB_STOP_TX 0x0000000a
  408. #define QE_USB_RESTART_TX 0x0000000c
  409. #define QE_QMC_STOP_TX 0x0000000c
  410. #define QE_QMC_STOP_RX 0x0000000d
  411. #define QE_SS7_SU_FIL_RESET 0x0000000e
  412. /* jonathbr added from here down for 83xx */
  413. #define QE_RESET_BCS 0x0000000a
  414. #define QE_MCC_INIT_TX_RX_16 0x00000003
  415. #define QE_MCC_STOP_TX 0x00000004
  416. #define QE_MCC_INIT_TX_1 0x00000005
  417. #define QE_MCC_INIT_RX_1 0x00000006
  418. #define QE_MCC_RESET 0x00000007
  419. #define QE_SET_TIMER 0x00000008
  420. #define QE_RANDOM_NUMBER 0x0000000c
  421. #define QE_ATM_MULTI_THREAD_INIT 0x00000011
  422. #define QE_ASSIGN_PAGE 0x00000012
  423. #define QE_ADD_REMOVE_HASH_ENTRY 0x00000013
  424. #define QE_START_FLOW_CONTROL 0x00000014
  425. #define QE_STOP_FLOW_CONTROL 0x00000015
  426. #define QE_ASSIGN_PAGE_TO_DEVICE 0x00000016
  427. #define QE_ASSIGN_RISC 0x00000010
  428. #define QE_CR_MCN_NORMAL_SHIFT 6
  429. #define QE_CR_MCN_USB_SHIFT 4
  430. #define QE_CR_MCN_RISC_ASSIGN_SHIFT 8
  431. #define QE_CR_SNUM_SHIFT 17
  432. /* QE CECR Sub Block - sub block of QE command.
  433. */
  434. #define QE_CR_SUBBLOCK_INVALID 0x00000000
  435. #define QE_CR_SUBBLOCK_USB 0x03200000
  436. #define QE_CR_SUBBLOCK_UCCFAST1 0x02000000
  437. #define QE_CR_SUBBLOCK_UCCFAST2 0x02200000
  438. #define QE_CR_SUBBLOCK_UCCFAST3 0x02400000
  439. #define QE_CR_SUBBLOCK_UCCFAST4 0x02600000
  440. #define QE_CR_SUBBLOCK_UCCFAST5 0x02800000
  441. #define QE_CR_SUBBLOCK_UCCFAST6 0x02a00000
  442. #define QE_CR_SUBBLOCK_UCCFAST7 0x02c00000
  443. #define QE_CR_SUBBLOCK_UCCFAST8 0x02e00000
  444. #define QE_CR_SUBBLOCK_UCCSLOW1 0x00000000
  445. #define QE_CR_SUBBLOCK_UCCSLOW2 0x00200000
  446. #define QE_CR_SUBBLOCK_UCCSLOW3 0x00400000
  447. #define QE_CR_SUBBLOCK_UCCSLOW4 0x00600000
  448. #define QE_CR_SUBBLOCK_UCCSLOW5 0x00800000
  449. #define QE_CR_SUBBLOCK_UCCSLOW6 0x00a00000
  450. #define QE_CR_SUBBLOCK_UCCSLOW7 0x00c00000
  451. #define QE_CR_SUBBLOCK_UCCSLOW8 0x00e00000
  452. #define QE_CR_SUBBLOCK_MCC1 0x03800000
  453. #define QE_CR_SUBBLOCK_MCC2 0x03a00000
  454. #define QE_CR_SUBBLOCK_MCC3 0x03000000
  455. #define QE_CR_SUBBLOCK_IDMA1 0x02800000
  456. #define QE_CR_SUBBLOCK_IDMA2 0x02a00000
  457. #define QE_CR_SUBBLOCK_IDMA3 0x02c00000
  458. #define QE_CR_SUBBLOCK_IDMA4 0x02e00000
  459. #define QE_CR_SUBBLOCK_HPAC 0x01e00000
  460. #define QE_CR_SUBBLOCK_SPI1 0x01400000
  461. #define QE_CR_SUBBLOCK_SPI2 0x01600000
  462. #define QE_CR_SUBBLOCK_RAND 0x01c00000
  463. #define QE_CR_SUBBLOCK_TIMER 0x01e00000
  464. #define QE_CR_SUBBLOCK_GENERAL 0x03c00000
  465. /* QE CECR Protocol - For non-MCC, specifies mode for QE CECR command */
  466. #define QE_CR_PROTOCOL_UNSPECIFIED 0x00 /* For all other protocols */
  467. #define QE_CR_PROTOCOL_HDLC_TRANSPARENT 0x00
  468. #define QE_CR_PROTOCOL_QMC 0x02
  469. #define QE_CR_PROTOCOL_UART 0x04
  470. #define QE_CR_PROTOCOL_ATM_POS 0x0A
  471. #define QE_CR_PROTOCOL_ETHERNET 0x0C
  472. #define QE_CR_PROTOCOL_L2_SWITCH 0x0D
  473. /* BRG configuration register */
  474. #define QE_BRGC_ENABLE 0x00010000
  475. #define QE_BRGC_DIVISOR_SHIFT 1
  476. #define QE_BRGC_DIVISOR_MAX 0xFFF
  477. #define QE_BRGC_DIV16 1
  478. /* QE Timers registers */
  479. #define QE_GTCFR1_PCAS 0x80
  480. #define QE_GTCFR1_STP2 0x20
  481. #define QE_GTCFR1_RST2 0x10
  482. #define QE_GTCFR1_GM2 0x08
  483. #define QE_GTCFR1_GM1 0x04
  484. #define QE_GTCFR1_STP1 0x02
  485. #define QE_GTCFR1_RST1 0x01
  486. /* SDMA registers */
  487. #define QE_SDSR_BER1 0x02000000
  488. #define QE_SDSR_BER2 0x01000000
  489. #define QE_SDMR_GLB_1_MSK 0x80000000
  490. #define QE_SDMR_ADR_SEL 0x20000000
  491. #define QE_SDMR_BER1_MSK 0x02000000
  492. #define QE_SDMR_BER2_MSK 0x01000000
  493. #define QE_SDMR_EB1_MSK 0x00800000
  494. #define QE_SDMR_ER1_MSK 0x00080000
  495. #define QE_SDMR_ER2_MSK 0x00040000
  496. #define QE_SDMR_CEN_MASK 0x0000E000
  497. #define QE_SDMR_SBER_1 0x00000200
  498. #define QE_SDMR_SBER_2 0x00000200
  499. #define QE_SDMR_EB1_PR_MASK 0x000000C0
  500. #define QE_SDMR_ER1_PR 0x00000008
  501. #define QE_SDMR_CEN_SHIFT 13
  502. #define QE_SDMR_EB1_PR_SHIFT 6
  503. #define QE_SDTM_MSNUM_SHIFT 24
  504. #define QE_SDEBCR_BA_MASK 0x01FFFFFF
  505. /* Communication Processor */
  506. #define QE_CP_CERCR_MEE 0x8000 /* Multi-user RAM ECC enable */
  507. #define QE_CP_CERCR_IEE 0x4000 /* Instruction RAM ECC enable */
  508. #define QE_CP_CERCR_CIR 0x0800 /* Common instruction RAM */
  509. /* I-RAM */
  510. #define QE_IRAM_IADD_AIE 0x80000000 /* Auto Increment Enable */
  511. #define QE_IRAM_IADD_BADDR 0x00080000 /* Base Address */
  512. #define QE_IRAM_READY 0x80000000 /* Ready */
  513. /* UPC */
  514. #define UPGCR_PROTOCOL 0x80000000 /* protocol ul2 or pl2 */
  515. #define UPGCR_TMS 0x40000000 /* Transmit master/slave mode */
  516. #define UPGCR_RMS 0x20000000 /* Receive master/slave mode */
  517. #define UPGCR_ADDR 0x10000000 /* Master MPHY Addr multiplexing */
  518. #define UPGCR_DIAG 0x01000000 /* Diagnostic mode */
  519. /* UCC GUEMR register */
  520. #define UCC_GUEMR_MODE_MASK_RX 0x02
  521. #define UCC_GUEMR_MODE_FAST_RX 0x02
  522. #define UCC_GUEMR_MODE_SLOW_RX 0x00
  523. #define UCC_GUEMR_MODE_MASK_TX 0x01
  524. #define UCC_GUEMR_MODE_FAST_TX 0x01
  525. #define UCC_GUEMR_MODE_SLOW_TX 0x00
  526. #define UCC_GUEMR_MODE_MASK (UCC_GUEMR_MODE_MASK_RX | UCC_GUEMR_MODE_MASK_TX)
  527. #define UCC_GUEMR_SET_RESERVED3 0x10 /* Bit 3 in the guemr is reserved but
  528. must be set 1 */
  529. /* structure representing UCC SLOW parameter RAM */
  530. struct ucc_slow_pram {
  531. __be16 rbase; /* RX BD base address */
  532. __be16 tbase; /* TX BD base address */
  533. u8 rbmr; /* RX bus mode register (same as CPM's RFCR) */
  534. u8 tbmr; /* TX bus mode register (same as CPM's TFCR) */
  535. __be16 mrblr; /* Rx buffer length */
  536. __be32 rstate; /* Rx internal state */
  537. __be32 rptr; /* Rx internal data pointer */
  538. __be16 rbptr; /* rb BD Pointer */
  539. __be16 rcount; /* Rx internal byte count */
  540. __be32 rtemp; /* Rx temp */
  541. __be32 tstate; /* Tx internal state */
  542. __be32 tptr; /* Tx internal data pointer */
  543. __be16 tbptr; /* Tx BD pointer */
  544. __be16 tcount; /* Tx byte count */
  545. __be32 ttemp; /* Tx temp */
  546. __be32 rcrc; /* temp receive CRC */
  547. __be32 tcrc; /* temp transmit CRC */
  548. } __attribute__ ((packed));
  549. /* General UCC SLOW Mode Register (GUMRH & GUMRL) */
  550. #define UCC_SLOW_GUMR_H_SAM_QMC 0x00000000
  551. #define UCC_SLOW_GUMR_H_SAM_SATM 0x00008000
  552. #define UCC_SLOW_GUMR_H_REVD 0x00002000
  553. #define UCC_SLOW_GUMR_H_TRX 0x00001000
  554. #define UCC_SLOW_GUMR_H_TTX 0x00000800
  555. #define UCC_SLOW_GUMR_H_CDP 0x00000400
  556. #define UCC_SLOW_GUMR_H_CTSP 0x00000200
  557. #define UCC_SLOW_GUMR_H_CDS 0x00000100
  558. #define UCC_SLOW_GUMR_H_CTSS 0x00000080
  559. #define UCC_SLOW_GUMR_H_TFL 0x00000040
  560. #define UCC_SLOW_GUMR_H_RFW 0x00000020
  561. #define UCC_SLOW_GUMR_H_TXSY 0x00000010
  562. #define UCC_SLOW_GUMR_H_4SYNC 0x00000004
  563. #define UCC_SLOW_GUMR_H_8SYNC 0x00000008
  564. #define UCC_SLOW_GUMR_H_16SYNC 0x0000000c
  565. #define UCC_SLOW_GUMR_H_RTSM 0x00000002
  566. #define UCC_SLOW_GUMR_H_RSYN 0x00000001
  567. #define UCC_SLOW_GUMR_L_TCI 0x10000000
  568. #define UCC_SLOW_GUMR_L_RINV 0x02000000
  569. #define UCC_SLOW_GUMR_L_TINV 0x01000000
  570. #define UCC_SLOW_GUMR_L_TEND 0x00040000
  571. #define UCC_SLOW_GUMR_L_TDCR_MASK 0x00030000
  572. #define UCC_SLOW_GUMR_L_TDCR_32 0x00030000
  573. #define UCC_SLOW_GUMR_L_TDCR_16 0x00020000
  574. #define UCC_SLOW_GUMR_L_TDCR_8 0x00010000
  575. #define UCC_SLOW_GUMR_L_TDCR_1 0x00000000
  576. #define UCC_SLOW_GUMR_L_RDCR_MASK 0x0000c000
  577. #define UCC_SLOW_GUMR_L_RDCR_32 0x0000c000
  578. #define UCC_SLOW_GUMR_L_RDCR_16 0x00008000
  579. #define UCC_SLOW_GUMR_L_RDCR_8 0x00004000
  580. #define UCC_SLOW_GUMR_L_RDCR_1 0x00000000
  581. #define UCC_SLOW_GUMR_L_RENC_NRZI 0x00000800
  582. #define UCC_SLOW_GUMR_L_RENC_NRZ 0x00000000
  583. #define UCC_SLOW_GUMR_L_TENC_NRZI 0x00000100
  584. #define UCC_SLOW_GUMR_L_TENC_NRZ 0x00000000
  585. #define UCC_SLOW_GUMR_L_DIAG_MASK 0x000000c0
  586. #define UCC_SLOW_GUMR_L_DIAG_LE 0x000000c0
  587. #define UCC_SLOW_GUMR_L_DIAG_ECHO 0x00000080
  588. #define UCC_SLOW_GUMR_L_DIAG_LOOP 0x00000040
  589. #define UCC_SLOW_GUMR_L_DIAG_NORM 0x00000000
  590. #define UCC_SLOW_GUMR_L_ENR 0x00000020
  591. #define UCC_SLOW_GUMR_L_ENT 0x00000010
  592. #define UCC_SLOW_GUMR_L_MODE_MASK 0x0000000F
  593. #define UCC_SLOW_GUMR_L_MODE_BISYNC 0x00000008
  594. #define UCC_SLOW_GUMR_L_MODE_AHDLC 0x00000006
  595. #define UCC_SLOW_GUMR_L_MODE_UART 0x00000004
  596. #define UCC_SLOW_GUMR_L_MODE_QMC 0x00000002
  597. /* General UCC FAST Mode Register */
  598. #define UCC_FAST_GUMR_LOOPBACK 0x40000000
  599. #define UCC_FAST_GUMR_TCI 0x20000000
  600. #define UCC_FAST_GUMR_TRX 0x10000000
  601. #define UCC_FAST_GUMR_TTX 0x08000000
  602. #define UCC_FAST_GUMR_CDP 0x04000000
  603. #define UCC_FAST_GUMR_CTSP 0x02000000
  604. #define UCC_FAST_GUMR_CDS 0x01000000
  605. #define UCC_FAST_GUMR_CTSS 0x00800000
  606. #define UCC_FAST_GUMR_TXSY 0x00020000
  607. #define UCC_FAST_GUMR_RSYN 0x00010000
  608. #define UCC_FAST_GUMR_RTSM 0x00002000
  609. #define UCC_FAST_GUMR_REVD 0x00000400
  610. #define UCC_FAST_GUMR_ENR 0x00000020
  611. #define UCC_FAST_GUMR_ENT 0x00000010
  612. /* UART Slow UCC Event Register (UCCE) */
  613. #define UCC_UART_UCCE_AB 0x0200
  614. #define UCC_UART_UCCE_IDLE 0x0100
  615. #define UCC_UART_UCCE_GRA 0x0080
  616. #define UCC_UART_UCCE_BRKE 0x0040
  617. #define UCC_UART_UCCE_BRKS 0x0020
  618. #define UCC_UART_UCCE_CCR 0x0008
  619. #define UCC_UART_UCCE_BSY 0x0004
  620. #define UCC_UART_UCCE_TX 0x0002
  621. #define UCC_UART_UCCE_RX 0x0001
  622. /* HDLC Slow UCC Event Register (UCCE) */
  623. #define UCC_HDLC_UCCE_GLR 0x1000
  624. #define UCC_HDLC_UCCE_GLT 0x0800
  625. #define UCC_HDLC_UCCE_IDLE 0x0100
  626. #define UCC_HDLC_UCCE_BRKE 0x0040
  627. #define UCC_HDLC_UCCE_BRKS 0x0020
  628. #define UCC_HDLC_UCCE_TXE 0x0010
  629. #define UCC_HDLC_UCCE_RXF 0x0008
  630. #define UCC_HDLC_UCCE_BSY 0x0004
  631. #define UCC_HDLC_UCCE_TXB 0x0002
  632. #define UCC_HDLC_UCCE_RXB 0x0001
  633. /* BISYNC Slow UCC Event Register (UCCE) */
  634. #define UCC_BISYNC_UCCE_GRA 0x0080
  635. #define UCC_BISYNC_UCCE_TXE 0x0010
  636. #define UCC_BISYNC_UCCE_RCH 0x0008
  637. #define UCC_BISYNC_UCCE_BSY 0x0004
  638. #define UCC_BISYNC_UCCE_TXB 0x0002
  639. #define UCC_BISYNC_UCCE_RXB 0x0001
  640. /* Gigabit Ethernet Fast UCC Event Register (UCCE) */
  641. #define UCC_GETH_UCCE_MPD 0x80000000
  642. #define UCC_GETH_UCCE_SCAR 0x40000000
  643. #define UCC_GETH_UCCE_GRA 0x20000000
  644. #define UCC_GETH_UCCE_CBPR 0x10000000
  645. #define UCC_GETH_UCCE_BSY 0x08000000
  646. #define UCC_GETH_UCCE_RXC 0x04000000
  647. #define UCC_GETH_UCCE_TXC 0x02000000
  648. #define UCC_GETH_UCCE_TXE 0x01000000
  649. #define UCC_GETH_UCCE_TXB7 0x00800000
  650. #define UCC_GETH_UCCE_TXB6 0x00400000
  651. #define UCC_GETH_UCCE_TXB5 0x00200000
  652. #define UCC_GETH_UCCE_TXB4 0x00100000
  653. #define UCC_GETH_UCCE_TXB3 0x00080000
  654. #define UCC_GETH_UCCE_TXB2 0x00040000
  655. #define UCC_GETH_UCCE_TXB1 0x00020000
  656. #define UCC_GETH_UCCE_TXB0 0x00010000
  657. #define UCC_GETH_UCCE_RXB7 0x00008000
  658. #define UCC_GETH_UCCE_RXB6 0x00004000
  659. #define UCC_GETH_UCCE_RXB5 0x00002000
  660. #define UCC_GETH_UCCE_RXB4 0x00001000
  661. #define UCC_GETH_UCCE_RXB3 0x00000800
  662. #define UCC_GETH_UCCE_RXB2 0x00000400
  663. #define UCC_GETH_UCCE_RXB1 0x00000200
  664. #define UCC_GETH_UCCE_RXB0 0x00000100
  665. #define UCC_GETH_UCCE_RXF7 0x00000080
  666. #define UCC_GETH_UCCE_RXF6 0x00000040
  667. #define UCC_GETH_UCCE_RXF5 0x00000020
  668. #define UCC_GETH_UCCE_RXF4 0x00000010
  669. #define UCC_GETH_UCCE_RXF3 0x00000008
  670. #define UCC_GETH_UCCE_RXF2 0x00000004
  671. #define UCC_GETH_UCCE_RXF1 0x00000002
  672. #define UCC_GETH_UCCE_RXF0 0x00000001
  673. /* UCC Protocol Specific Mode Register (UPSMR), when used for UART */
  674. #define UCC_UART_UPSMR_FLC 0x8000
  675. #define UCC_UART_UPSMR_SL 0x4000
  676. #define UCC_UART_UPSMR_CL_MASK 0x3000
  677. #define UCC_UART_UPSMR_CL_8 0x3000
  678. #define UCC_UART_UPSMR_CL_7 0x2000
  679. #define UCC_UART_UPSMR_CL_6 0x1000
  680. #define UCC_UART_UPSMR_CL_5 0x0000
  681. #define UCC_UART_UPSMR_UM_MASK 0x0c00
  682. #define UCC_UART_UPSMR_UM_NORMAL 0x0000
  683. #define UCC_UART_UPSMR_UM_MAN_MULTI 0x0400
  684. #define UCC_UART_UPSMR_UM_AUTO_MULTI 0x0c00
  685. #define UCC_UART_UPSMR_FRZ 0x0200
  686. #define UCC_UART_UPSMR_RZS 0x0100
  687. #define UCC_UART_UPSMR_SYN 0x0080
  688. #define UCC_UART_UPSMR_DRT 0x0040
  689. #define UCC_UART_UPSMR_PEN 0x0010
  690. #define UCC_UART_UPSMR_RPM_MASK 0x000c
  691. #define UCC_UART_UPSMR_RPM_ODD 0x0000
  692. #define UCC_UART_UPSMR_RPM_LOW 0x0004
  693. #define UCC_UART_UPSMR_RPM_EVEN 0x0008
  694. #define UCC_UART_UPSMR_RPM_HIGH 0x000C
  695. #define UCC_UART_UPSMR_TPM_MASK 0x0003
  696. #define UCC_UART_UPSMR_TPM_ODD 0x0000
  697. #define UCC_UART_UPSMR_TPM_LOW 0x0001
  698. #define UCC_UART_UPSMR_TPM_EVEN 0x0002
  699. #define UCC_UART_UPSMR_TPM_HIGH 0x0003
  700. /* UCC Protocol Specific Mode Register (UPSMR), when used for Ethernet */
  701. #define UCC_GETH_UPSMR_FTFE 0x80000000
  702. #define UCC_GETH_UPSMR_PTPE 0x40000000
  703. #define UCC_GETH_UPSMR_ECM 0x04000000
  704. #define UCC_GETH_UPSMR_HSE 0x02000000
  705. #define UCC_GETH_UPSMR_PRO 0x00400000
  706. #define UCC_GETH_UPSMR_CAP 0x00200000
  707. #define UCC_GETH_UPSMR_RSH 0x00100000
  708. #define UCC_GETH_UPSMR_RPM 0x00080000
  709. #define UCC_GETH_UPSMR_R10M 0x00040000
  710. #define UCC_GETH_UPSMR_RLPB 0x00020000
  711. #define UCC_GETH_UPSMR_TBIM 0x00010000
  712. #define UCC_GETH_UPSMR_RES1 0x00002000
  713. #define UCC_GETH_UPSMR_RMM 0x00001000
  714. #define UCC_GETH_UPSMR_CAM 0x00000400
  715. #define UCC_GETH_UPSMR_BRO 0x00000200
  716. #define UCC_GETH_UPSMR_SMM 0x00000080
  717. #define UCC_GETH_UPSMR_SGMM 0x00000020
  718. /* UCC Transmit On Demand Register (UTODR) */
  719. #define UCC_SLOW_TOD 0x8000
  720. #define UCC_FAST_TOD 0x8000
  721. /* UCC Bus Mode Register masks */
  722. /* Not to be confused with the Bundle Mode Register */
  723. #define UCC_BMR_GBL 0x20
  724. #define UCC_BMR_BO_BE 0x10
  725. #define UCC_BMR_CETM 0x04
  726. #define UCC_BMR_DTB 0x02
  727. #define UCC_BMR_BDB 0x01
  728. /* Function code masks */
  729. #define FC_GBL 0x20
  730. #define FC_DTB_LCL 0x02
  731. #define UCC_FAST_FUNCTION_CODE_GBL 0x20
  732. #define UCC_FAST_FUNCTION_CODE_DTB_LCL 0x02
  733. #define UCC_FAST_FUNCTION_CODE_BDB_LCL 0x01
  734. #endif /* __KERNEL__ */
  735. #endif /* _ASM_POWERPC_QE_H */