pmic.h 27 KB

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  1. /*
  2. * pmic.h -- Power Management Driver for Wolfson WM8350 PMIC
  3. *
  4. * Copyright 2007 Wolfson Microelectronics PLC
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the
  8. * Free Software Foundation; either version 2 of the License, or (at your
  9. * option) any later version.
  10. *
  11. */
  12. #ifndef __LINUX_MFD_WM8350_PMIC_H
  13. #define __LINUX_MFD_WM8350_PMIC_H
  14. #include <linux/platform_device.h>
  15. #include <linux/leds.h>
  16. #include <linux/regulator/machine.h>
  17. /*
  18. * Register values.
  19. */
  20. #define WM8350_CURRENT_SINK_DRIVER_A 0xAC
  21. #define WM8350_CSA_FLASH_CONTROL 0xAD
  22. #define WM8350_CURRENT_SINK_DRIVER_B 0xAE
  23. #define WM8350_CSB_FLASH_CONTROL 0xAF
  24. #define WM8350_DCDC_LDO_REQUESTED 0xB0
  25. #define WM8350_DCDC_ACTIVE_OPTIONS 0xB1
  26. #define WM8350_DCDC_SLEEP_OPTIONS 0xB2
  27. #define WM8350_POWER_CHECK_COMPARATOR 0xB3
  28. #define WM8350_DCDC1_CONTROL 0xB4
  29. #define WM8350_DCDC1_TIMEOUTS 0xB5
  30. #define WM8350_DCDC1_LOW_POWER 0xB6
  31. #define WM8350_DCDC2_CONTROL 0xB7
  32. #define WM8350_DCDC2_TIMEOUTS 0xB8
  33. #define WM8350_DCDC3_CONTROL 0xBA
  34. #define WM8350_DCDC3_TIMEOUTS 0xBB
  35. #define WM8350_DCDC3_LOW_POWER 0xBC
  36. #define WM8350_DCDC4_CONTROL 0xBD
  37. #define WM8350_DCDC4_TIMEOUTS 0xBE
  38. #define WM8350_DCDC4_LOW_POWER 0xBF
  39. #define WM8350_DCDC5_CONTROL 0xC0
  40. #define WM8350_DCDC5_TIMEOUTS 0xC1
  41. #define WM8350_DCDC6_CONTROL 0xC3
  42. #define WM8350_DCDC6_TIMEOUTS 0xC4
  43. #define WM8350_DCDC6_LOW_POWER 0xC5
  44. #define WM8350_LIMIT_SWITCH_CONTROL 0xC7
  45. #define WM8350_LDO1_CONTROL 0xC8
  46. #define WM8350_LDO1_TIMEOUTS 0xC9
  47. #define WM8350_LDO1_LOW_POWER 0xCA
  48. #define WM8350_LDO2_CONTROL 0xCB
  49. #define WM8350_LDO2_TIMEOUTS 0xCC
  50. #define WM8350_LDO2_LOW_POWER 0xCD
  51. #define WM8350_LDO3_CONTROL 0xCE
  52. #define WM8350_LDO3_TIMEOUTS 0xCF
  53. #define WM8350_LDO3_LOW_POWER 0xD0
  54. #define WM8350_LDO4_CONTROL 0xD1
  55. #define WM8350_LDO4_TIMEOUTS 0xD2
  56. #define WM8350_LDO4_LOW_POWER 0xD3
  57. #define WM8350_VCC_FAULT_MASKS 0xD7
  58. #define WM8350_MAIN_BANDGAP_CONTROL 0xD8
  59. #define WM8350_OSC_CONTROL 0xD9
  60. #define WM8350_RTC_TICK_CONTROL 0xDA
  61. #define WM8350_SECURITY 0xDB
  62. #define WM8350_RAM_BIST_1 0xDC
  63. #define WM8350_DCDC_LDO_STATUS 0xE1
  64. #define WM8350_GPIO_PIN_STATUS 0xE6
  65. #define WM8350_DCDC1_FORCE_PWM 0xF8
  66. #define WM8350_DCDC3_FORCE_PWM 0xFA
  67. #define WM8350_DCDC4_FORCE_PWM 0xFB
  68. #define WM8350_DCDC6_FORCE_PWM 0xFD
  69. /*
  70. * R172 (0xAC) - Current Sink Driver A
  71. */
  72. #define WM8350_CS1_HIB_MODE 0x1000
  73. #define WM8350_CS1_HIB_MODE_MASK 0x1000
  74. #define WM8350_CS1_HIB_MODE_SHIFT 12
  75. #define WM8350_CS1_ISEL_MASK 0x003F
  76. #define WM8350_CS1_ISEL_SHIFT 0
  77. /* Bit values for R172 (0xAC) */
  78. #define WM8350_CS1_HIB_MODE_DISABLE 0
  79. #define WM8350_CS1_HIB_MODE_LEAVE 1
  80. #define WM8350_CS1_ISEL_220M 0x3F
  81. /*
  82. * R173 (0xAD) - CSA Flash control
  83. */
  84. #define WM8350_CS1_FLASH_MODE 0x8000
  85. #define WM8350_CS1_TRIGSRC 0x4000
  86. #define WM8350_CS1_DRIVE 0x2000
  87. #define WM8350_CS1_FLASH_DUR_MASK 0x0300
  88. #define WM8350_CS1_OFF_RAMP_MASK 0x0030
  89. #define WM8350_CS1_ON_RAMP_MASK 0x0003
  90. /*
  91. * R174 (0xAE) - Current Sink Driver B
  92. */
  93. #define WM8350_CS2_HIB_MODE 0x1000
  94. #define WM8350_CS2_ISEL_MASK 0x003F
  95. /*
  96. * R175 (0xAF) - CSB Flash control
  97. */
  98. #define WM8350_CS2_FLASH_MODE 0x8000
  99. #define WM8350_CS2_TRIGSRC 0x4000
  100. #define WM8350_CS2_DRIVE 0x2000
  101. #define WM8350_CS2_FLASH_DUR_MASK 0x0300
  102. #define WM8350_CS2_OFF_RAMP_MASK 0x0030
  103. #define WM8350_CS2_ON_RAMP_MASK 0x0003
  104. /*
  105. * R176 (0xB0) - DCDC/LDO requested
  106. */
  107. #define WM8350_LS_ENA 0x8000
  108. #define WM8350_LDO4_ENA 0x0800
  109. #define WM8350_LDO3_ENA 0x0400
  110. #define WM8350_LDO2_ENA 0x0200
  111. #define WM8350_LDO1_ENA 0x0100
  112. #define WM8350_DC6_ENA 0x0020
  113. #define WM8350_DC5_ENA 0x0010
  114. #define WM8350_DC4_ENA 0x0008
  115. #define WM8350_DC3_ENA 0x0004
  116. #define WM8350_DC2_ENA 0x0002
  117. #define WM8350_DC1_ENA 0x0001
  118. /*
  119. * R177 (0xB1) - DCDC Active options
  120. */
  121. #define WM8350_PUTO_MASK 0x3000
  122. #define WM8350_PWRUP_DELAY_MASK 0x0300
  123. #define WM8350_DC6_ACTIVE 0x0020
  124. #define WM8350_DC4_ACTIVE 0x0008
  125. #define WM8350_DC3_ACTIVE 0x0004
  126. #define WM8350_DC1_ACTIVE 0x0001
  127. /*
  128. * R178 (0xB2) - DCDC Sleep options
  129. */
  130. #define WM8350_DC6_SLEEP 0x0020
  131. #define WM8350_DC4_SLEEP 0x0008
  132. #define WM8350_DC3_SLEEP 0x0004
  133. #define WM8350_DC1_SLEEP 0x0001
  134. /*
  135. * R179 (0xB3) - Power-check comparator
  136. */
  137. #define WM8350_PCCMP_ERRACT 0x4000
  138. #define WM8350_PCCMP_RAIL 0x0100
  139. #define WM8350_PCCMP_OFF_THR_MASK 0x0070
  140. #define WM8350_PCCMP_ON_THR_MASK 0x0007
  141. /*
  142. * R180 (0xB4) - DCDC1 Control
  143. */
  144. #define WM8350_DC1_OPFLT 0x0400
  145. #define WM8350_DC1_VSEL_MASK 0x007F
  146. #define WM8350_DC1_VSEL_SHIFT 0
  147. /*
  148. * R181 (0xB5) - DCDC1 Timeouts
  149. */
  150. #define WM8350_DC1_ERRACT_MASK 0xC000
  151. #define WM8350_DC1_ERRACT_SHIFT 14
  152. #define WM8350_DC1_ENSLOT_MASK 0x3C00
  153. #define WM8350_DC1_ENSLOT_SHIFT 10
  154. #define WM8350_DC1_SDSLOT_MASK 0x03C0
  155. #define WM8350_DC1_UVTO_MASK 0x0030
  156. #define WM8350_DC1_SDSLOT_SHIFT 6
  157. /* Bit values for R181 (0xB5) */
  158. #define WM8350_DC1_ERRACT_NONE 0
  159. #define WM8350_DC1_ERRACT_SHUTDOWN_CONV 1
  160. #define WM8350_DC1_ERRACT_SHUTDOWN_SYS 2
  161. /*
  162. * R182 (0xB6) - DCDC1 Low Power
  163. */
  164. #define WM8350_DC1_HIB_MODE_MASK 0x7000
  165. #define WM8350_DC1_HIB_TRIG_MASK 0x0300
  166. #define WM8350_DC1_VIMG_MASK 0x007F
  167. /*
  168. * R183 (0xB7) - DCDC2 Control
  169. */
  170. #define WM8350_DC2_MODE 0x4000
  171. #define WM8350_DC2_MODE_MASK 0x4000
  172. #define WM8350_DC2_MODE_SHIFT 14
  173. #define WM8350_DC2_HIB_MODE 0x1000
  174. #define WM8350_DC2_HIB_MODE_MASK 0x1000
  175. #define WM8350_DC2_HIB_MODE_SHIFT 12
  176. #define WM8350_DC2_HIB_TRIG_MASK 0x0300
  177. #define WM8350_DC2_HIB_TRIG_SHIFT 8
  178. #define WM8350_DC2_ILIM 0x0040
  179. #define WM8350_DC2_ILIM_MASK 0x0040
  180. #define WM8350_DC2_ILIM_SHIFT 6
  181. #define WM8350_DC2_RMP_MASK 0x0018
  182. #define WM8350_DC2_RMP_SHIFT 3
  183. #define WM8350_DC2_FBSRC_MASK 0x0003
  184. #define WM8350_DC2_FBSRC_SHIFT 0
  185. /* Bit values for R183 (0xB7) */
  186. #define WM8350_DC2_MODE_BOOST 0
  187. #define WM8350_DC2_MODE_SWITCH 1
  188. #define WM8350_DC2_HIB_MODE_ACTIVE 1
  189. #define WM8350_DC2_HIB_MODE_DISABLE 0
  190. #define WM8350_DC2_HIB_TRIG_NONE 0
  191. #define WM8350_DC2_HIB_TRIG_LPWR1 1
  192. #define WM8350_DC2_HIB_TRIG_LPWR2 2
  193. #define WM8350_DC2_HIB_TRIG_LPWR3 3
  194. #define WM8350_DC2_ILIM_HIGH 0
  195. #define WM8350_DC2_ILIM_LOW 1
  196. #define WM8350_DC2_RMP_30V 0
  197. #define WM8350_DC2_RMP_20V 1
  198. #define WM8350_DC2_RMP_10V 2
  199. #define WM8350_DC2_RMP_5V 3
  200. #define WM8350_DC2_FBSRC_FB2 0
  201. #define WM8350_DC2_FBSRC_ISINKA 1
  202. #define WM8350_DC2_FBSRC_ISINKB 2
  203. #define WM8350_DC2_FBSRC_USB 3
  204. /*
  205. * R184 (0xB8) - DCDC2 Timeouts
  206. */
  207. #define WM8350_DC2_ERRACT_MASK 0xC000
  208. #define WM8350_DC2_ERRACT_SHIFT 14
  209. #define WM8350_DC2_ENSLOT_MASK 0x3C00
  210. #define WM8350_DC2_ENSLOT_SHIFT 10
  211. #define WM8350_DC2_SDSLOT_MASK 0x03C0
  212. #define WM8350_DC2_UVTO_MASK 0x0030
  213. /* Bit values for R184 (0xB8) */
  214. #define WM8350_DC2_ERRACT_NONE 0
  215. #define WM8350_DC2_ERRACT_SHUTDOWN_CONV 1
  216. #define WM8350_DC2_ERRACT_SHUTDOWN_SYS 2
  217. /*
  218. * R186 (0xBA) - DCDC3 Control
  219. */
  220. #define WM8350_DC3_OPFLT 0x0400
  221. #define WM8350_DC3_VSEL_MASK 0x007F
  222. #define WM8350_DC3_VSEL_SHIFT 0
  223. /*
  224. * R187 (0xBB) - DCDC3 Timeouts
  225. */
  226. #define WM8350_DC3_ERRACT_MASK 0xC000
  227. #define WM8350_DC3_ERRACT_SHIFT 14
  228. #define WM8350_DC3_ENSLOT_MASK 0x3C00
  229. #define WM8350_DC3_ENSLOT_SHIFT 10
  230. #define WM8350_DC3_SDSLOT_MASK 0x03C0
  231. #define WM8350_DC3_UVTO_MASK 0x0030
  232. #define WM8350_DC3_SDSLOT_SHIFT 6
  233. /* Bit values for R187 (0xBB) */
  234. #define WM8350_DC3_ERRACT_NONE 0
  235. #define WM8350_DC3_ERRACT_SHUTDOWN_CONV 1
  236. #define WM8350_DC3_ERRACT_SHUTDOWN_SYS 2
  237. /*
  238. * R188 (0xBC) - DCDC3 Low Power
  239. */
  240. #define WM8350_DC3_HIB_MODE_MASK 0x7000
  241. #define WM8350_DC3_HIB_TRIG_MASK 0x0300
  242. #define WM8350_DC3_VIMG_MASK 0x007F
  243. /*
  244. * R189 (0xBD) - DCDC4 Control
  245. */
  246. #define WM8350_DC4_OPFLT 0x0400
  247. #define WM8350_DC4_VSEL_MASK 0x007F
  248. #define WM8350_DC4_VSEL_SHIFT 0
  249. /*
  250. * R190 (0xBE) - DCDC4 Timeouts
  251. */
  252. #define WM8350_DC4_ERRACT_MASK 0xC000
  253. #define WM8350_DC4_ERRACT_SHIFT 14
  254. #define WM8350_DC4_ENSLOT_MASK 0x3C00
  255. #define WM8350_DC4_ENSLOT_SHIFT 10
  256. #define WM8350_DC4_SDSLOT_MASK 0x03C0
  257. #define WM8350_DC4_UVTO_MASK 0x0030
  258. #define WM8350_DC4_SDSLOT_SHIFT 6
  259. /* Bit values for R190 (0xBE) */
  260. #define WM8350_DC4_ERRACT_NONE 0
  261. #define WM8350_DC4_ERRACT_SHUTDOWN_CONV 1
  262. #define WM8350_DC4_ERRACT_SHUTDOWN_SYS 2
  263. /*
  264. * R191 (0xBF) - DCDC4 Low Power
  265. */
  266. #define WM8350_DC4_HIB_MODE_MASK 0x7000
  267. #define WM8350_DC4_HIB_TRIG_MASK 0x0300
  268. #define WM8350_DC4_VIMG_MASK 0x007F
  269. /*
  270. * R192 (0xC0) - DCDC5 Control
  271. */
  272. #define WM8350_DC5_MODE 0x4000
  273. #define WM8350_DC5_MODE_MASK 0x4000
  274. #define WM8350_DC5_MODE_SHIFT 14
  275. #define WM8350_DC5_HIB_MODE 0x1000
  276. #define WM8350_DC5_HIB_MODE_MASK 0x1000
  277. #define WM8350_DC5_HIB_MODE_SHIFT 12
  278. #define WM8350_DC5_HIB_TRIG_MASK 0x0300
  279. #define WM8350_DC5_HIB_TRIG_SHIFT 8
  280. #define WM8350_DC5_ILIM 0x0040
  281. #define WM8350_DC5_ILIM_MASK 0x0040
  282. #define WM8350_DC5_ILIM_SHIFT 6
  283. #define WM8350_DC5_RMP_MASK 0x0018
  284. #define WM8350_DC5_RMP_SHIFT 3
  285. #define WM8350_DC5_FBSRC_MASK 0x0003
  286. #define WM8350_DC5_FBSRC_SHIFT 0
  287. /* Bit values for R192 (0xC0) */
  288. #define WM8350_DC5_MODE_BOOST 0
  289. #define WM8350_DC5_MODE_SWITCH 1
  290. #define WM8350_DC5_HIB_MODE_ACTIVE 1
  291. #define WM8350_DC5_HIB_MODE_DISABLE 0
  292. #define WM8350_DC5_HIB_TRIG_NONE 0
  293. #define WM8350_DC5_HIB_TRIG_LPWR1 1
  294. #define WM8350_DC5_HIB_TRIG_LPWR2 2
  295. #define WM8350_DC5_HIB_TRIG_LPWR3 3
  296. #define WM8350_DC5_ILIM_HIGH 0
  297. #define WM8350_DC5_ILIM_LOW 1
  298. #define WM8350_DC5_RMP_30V 0
  299. #define WM8350_DC5_RMP_20V 1
  300. #define WM8350_DC5_RMP_10V 2
  301. #define WM8350_DC5_RMP_5V 3
  302. #define WM8350_DC5_FBSRC_FB2 0
  303. #define WM8350_DC5_FBSRC_ISINKA 1
  304. #define WM8350_DC5_FBSRC_ISINKB 2
  305. #define WM8350_DC5_FBSRC_USB 3
  306. /*
  307. * R193 (0xC1) - DCDC5 Timeouts
  308. */
  309. #define WM8350_DC5_ERRACT_MASK 0xC000
  310. #define WM8350_DC5_ERRACT_SHIFT 14
  311. #define WM8350_DC5_ENSLOT_MASK 0x3C00
  312. #define WM8350_DC5_ENSLOT_SHIFT 10
  313. #define WM8350_DC5_SDSLOT_MASK 0x03C0
  314. #define WM8350_DC5_UVTO_MASK 0x0030
  315. #define WM8350_DC5_SDSLOT_SHIFT 6
  316. /* Bit values for R193 (0xC1) */
  317. #define WM8350_DC5_ERRACT_NONE 0
  318. #define WM8350_DC5_ERRACT_SHUTDOWN_CONV 1
  319. #define WM8350_DC5_ERRACT_SHUTDOWN_SYS 2
  320. /*
  321. * R195 (0xC3) - DCDC6 Control
  322. */
  323. #define WM8350_DC6_OPFLT 0x0400
  324. #define WM8350_DC6_VSEL_MASK 0x007F
  325. #define WM8350_DC6_VSEL_SHIFT 0
  326. /*
  327. * R196 (0xC4) - DCDC6 Timeouts
  328. */
  329. #define WM8350_DC6_ERRACT_MASK 0xC000
  330. #define WM8350_DC6_ERRACT_SHIFT 14
  331. #define WM8350_DC6_ENSLOT_MASK 0x3C00
  332. #define WM8350_DC6_ENSLOT_SHIFT 10
  333. #define WM8350_DC6_SDSLOT_MASK 0x03C0
  334. #define WM8350_DC6_UVTO_MASK 0x0030
  335. #define WM8350_DC6_SDSLOT_SHIFT 6
  336. /* Bit values for R196 (0xC4) */
  337. #define WM8350_DC6_ERRACT_NONE 0
  338. #define WM8350_DC6_ERRACT_SHUTDOWN_CONV 1
  339. #define WM8350_DC6_ERRACT_SHUTDOWN_SYS 2
  340. /*
  341. * R197 (0xC5) - DCDC6 Low Power
  342. */
  343. #define WM8350_DC6_HIB_MODE_MASK 0x7000
  344. #define WM8350_DC6_HIB_TRIG_MASK 0x0300
  345. #define WM8350_DC6_VIMG_MASK 0x007F
  346. /*
  347. * R199 (0xC7) - Limit Switch Control
  348. */
  349. #define WM8350_LS_ERRACT_MASK 0xC000
  350. #define WM8350_LS_ERRACT_SHIFT 14
  351. #define WM8350_LS_ENSLOT_MASK 0x3C00
  352. #define WM8350_LS_ENSLOT_SHIFT 10
  353. #define WM8350_LS_SDSLOT_MASK 0x03C0
  354. #define WM8350_LS_SDSLOT_SHIFT 6
  355. #define WM8350_LS_HIB_MODE 0x0010
  356. #define WM8350_LS_HIB_MODE_MASK 0x0010
  357. #define WM8350_LS_HIB_MODE_SHIFT 4
  358. #define WM8350_LS_HIB_PROT 0x0002
  359. #define WM8350_LS_HIB_PROT_MASK 0x0002
  360. #define WM8350_LS_HIB_PROT_SHIFT 1
  361. #define WM8350_LS_PROT 0x0001
  362. #define WM8350_LS_PROT_MASK 0x0001
  363. #define WM8350_LS_PROT_SHIFT 0
  364. /* Bit values for R199 (0xC7) */
  365. #define WM8350_LS_ERRACT_NONE 0
  366. #define WM8350_LS_ERRACT_SHUTDOWN_CONV 1
  367. #define WM8350_LS_ERRACT_SHUTDOWN_SYS 2
  368. /*
  369. * R200 (0xC8) - LDO1 Control
  370. */
  371. #define WM8350_LDO1_SWI 0x4000
  372. #define WM8350_LDO1_OPFLT 0x0400
  373. #define WM8350_LDO1_VSEL_MASK 0x001F
  374. #define WM8350_LDO1_VSEL_SHIFT 0
  375. /*
  376. * R201 (0xC9) - LDO1 Timeouts
  377. */
  378. #define WM8350_LDO1_ERRACT_MASK 0xC000
  379. #define WM8350_LDO1_ERRACT_SHIFT 14
  380. #define WM8350_LDO1_ENSLOT_MASK 0x3C00
  381. #define WM8350_LDO1_ENSLOT_SHIFT 10
  382. #define WM8350_LDO1_SDSLOT_MASK 0x03C0
  383. #define WM8350_LDO1_UVTO_MASK 0x0030
  384. #define WM8350_LDO1_SDSLOT_SHIFT 6
  385. /* Bit values for R201 (0xC9) */
  386. #define WM8350_LDO1_ERRACT_NONE 0
  387. #define WM8350_LDO1_ERRACT_SHUTDOWN_CONV 1
  388. #define WM8350_LDO1_ERRACT_SHUTDOWN_SYS 2
  389. /*
  390. * R202 (0xCA) - LDO1 Low Power
  391. */
  392. #define WM8350_LDO1_HIB_MODE_MASK 0x3000
  393. #define WM8350_LDO1_HIB_TRIG_MASK 0x0300
  394. #define WM8350_LDO1_VIMG_MASK 0x001F
  395. #define WM8350_LDO1_HIB_MODE_DIS (0x1 << 12)
  396. /*
  397. * R203 (0xCB) - LDO2 Control
  398. */
  399. #define WM8350_LDO2_SWI 0x4000
  400. #define WM8350_LDO2_OPFLT 0x0400
  401. #define WM8350_LDO2_VSEL_MASK 0x001F
  402. #define WM8350_LDO2_VSEL_SHIFT 0
  403. /*
  404. * R204 (0xCC) - LDO2 Timeouts
  405. */
  406. #define WM8350_LDO2_ERRACT_MASK 0xC000
  407. #define WM8350_LDO2_ERRACT_SHIFT 14
  408. #define WM8350_LDO2_ENSLOT_MASK 0x3C00
  409. #define WM8350_LDO2_ENSLOT_SHIFT 10
  410. #define WM8350_LDO2_SDSLOT_MASK 0x03C0
  411. #define WM8350_LDO2_SDSLOT_SHIFT 6
  412. /* Bit values for R204 (0xCC) */
  413. #define WM8350_LDO2_ERRACT_NONE 0
  414. #define WM8350_LDO2_ERRACT_SHUTDOWN_CONV 1
  415. #define WM8350_LDO2_ERRACT_SHUTDOWN_SYS 2
  416. /*
  417. * R205 (0xCD) - LDO2 Low Power
  418. */
  419. #define WM8350_LDO2_HIB_MODE_MASK 0x3000
  420. #define WM8350_LDO2_HIB_TRIG_MASK 0x0300
  421. #define WM8350_LDO2_VIMG_MASK 0x001F
  422. /*
  423. * R206 (0xCE) - LDO3 Control
  424. */
  425. #define WM8350_LDO3_SWI 0x4000
  426. #define WM8350_LDO3_OPFLT 0x0400
  427. #define WM8350_LDO3_VSEL_MASK 0x001F
  428. #define WM8350_LDO3_VSEL_SHIFT 0
  429. /*
  430. * R207 (0xCF) - LDO3 Timeouts
  431. */
  432. #define WM8350_LDO3_ERRACT_MASK 0xC000
  433. #define WM8350_LDO3_ERRACT_SHIFT 14
  434. #define WM8350_LDO3_ENSLOT_MASK 0x3C00
  435. #define WM8350_LDO3_ENSLOT_SHIFT 10
  436. #define WM8350_LDO3_SDSLOT_MASK 0x03C0
  437. #define WM8350_LDO3_UVTO_MASK 0x0030
  438. #define WM8350_LDO3_SDSLOT_SHIFT 6
  439. /* Bit values for R207 (0xCF) */
  440. #define WM8350_LDO3_ERRACT_NONE 0
  441. #define WM8350_LDO3_ERRACT_SHUTDOWN_CONV 1
  442. #define WM8350_LDO3_ERRACT_SHUTDOWN_SYS 2
  443. /*
  444. * R208 (0xD0) - LDO3 Low Power
  445. */
  446. #define WM8350_LDO3_HIB_MODE_MASK 0x3000
  447. #define WM8350_LDO3_HIB_TRIG_MASK 0x0300
  448. #define WM8350_LDO3_VIMG_MASK 0x001F
  449. /*
  450. * R209 (0xD1) - LDO4 Control
  451. */
  452. #define WM8350_LDO4_SWI 0x4000
  453. #define WM8350_LDO4_OPFLT 0x0400
  454. #define WM8350_LDO4_VSEL_MASK 0x001F
  455. #define WM8350_LDO4_VSEL_SHIFT 0
  456. /*
  457. * R210 (0xD2) - LDO4 Timeouts
  458. */
  459. #define WM8350_LDO4_ERRACT_MASK 0xC000
  460. #define WM8350_LDO4_ERRACT_SHIFT 14
  461. #define WM8350_LDO4_ENSLOT_MASK 0x3C00
  462. #define WM8350_LDO4_ENSLOT_SHIFT 10
  463. #define WM8350_LDO4_SDSLOT_MASK 0x03C0
  464. #define WM8350_LDO4_UVTO_MASK 0x0030
  465. #define WM8350_LDO4_SDSLOT_SHIFT 6
  466. /* Bit values for R210 (0xD2) */
  467. #define WM8350_LDO4_ERRACT_NONE 0
  468. #define WM8350_LDO4_ERRACT_SHUTDOWN_CONV 1
  469. #define WM8350_LDO4_ERRACT_SHUTDOWN_SYS 2
  470. /*
  471. * R211 (0xD3) - LDO4 Low Power
  472. */
  473. #define WM8350_LDO4_HIB_MODE_MASK 0x3000
  474. #define WM8350_LDO4_HIB_TRIG_MASK 0x0300
  475. #define WM8350_LDO4_VIMG_MASK 0x001F
  476. /*
  477. * R215 (0xD7) - VCC_FAULT Masks
  478. */
  479. #define WM8350_LS_FAULT 0x8000
  480. #define WM8350_LDO4_FAULT 0x0800
  481. #define WM8350_LDO3_FAULT 0x0400
  482. #define WM8350_LDO2_FAULT 0x0200
  483. #define WM8350_LDO1_FAULT 0x0100
  484. #define WM8350_DC6_FAULT 0x0020
  485. #define WM8350_DC5_FAULT 0x0010
  486. #define WM8350_DC4_FAULT 0x0008
  487. #define WM8350_DC3_FAULT 0x0004
  488. #define WM8350_DC2_FAULT 0x0002
  489. #define WM8350_DC1_FAULT 0x0001
  490. /*
  491. * R216 (0xD8) - Main Bandgap Control
  492. */
  493. #define WM8350_MBG_LOAD_FUSES 0x8000
  494. #define WM8350_MBG_FUSE_WPREP 0x4000
  495. #define WM8350_MBG_FUSE_WRITE 0x2000
  496. #define WM8350_MBG_FUSE_TRIM_MASK 0x1F00
  497. #define WM8350_MBG_TRIM_SRC 0x0020
  498. #define WM8350_MBG_USER_TRIM_MASK 0x001F
  499. /*
  500. * R217 (0xD9) - OSC Control
  501. */
  502. #define WM8350_OSC_LOAD_FUSES 0x8000
  503. #define WM8350_OSC_FUSE_WPREP 0x4000
  504. #define WM8350_OSC_FUSE_WRITE 0x2000
  505. #define WM8350_OSC_FUSE_TRIM_MASK 0x0F00
  506. #define WM8350_OSC_TRIM_SRC 0x0020
  507. #define WM8350_OSC_USER_TRIM_MASK 0x000F
  508. /*
  509. * R248 (0xF8) - DCDC1 Force PWM
  510. */
  511. #define WM8350_DCDC1_FORCE_PWM_ENA 0x0010
  512. /*
  513. * R250 (0xFA) - DCDC3 Force PWM
  514. */
  515. #define WM8350_DCDC3_FORCE_PWM_ENA 0x0010
  516. /*
  517. * R251 (0xFB) - DCDC4 Force PWM
  518. */
  519. #define WM8350_DCDC4_FORCE_PWM_ENA 0x0010
  520. /*
  521. * R253 (0xFD) - DCDC1 Force PWM
  522. */
  523. #define WM8350_DCDC6_FORCE_PWM_ENA 0x0010
  524. /*
  525. * DCDC's
  526. */
  527. #define WM8350_DCDC_1 0
  528. #define WM8350_DCDC_2 1
  529. #define WM8350_DCDC_3 2
  530. #define WM8350_DCDC_4 3
  531. #define WM8350_DCDC_5 4
  532. #define WM8350_DCDC_6 5
  533. /* DCDC modes */
  534. #define WM8350_DCDC_ACTIVE_STANDBY 0
  535. #define WM8350_DCDC_ACTIVE_PULSE 1
  536. #define WM8350_DCDC_SLEEP_NORMAL 0
  537. #define WM8350_DCDC_SLEEP_LOW 1
  538. /* DCDC Low power (Hibernate) mode */
  539. #define WM8350_DCDC_HIB_MODE_CUR (0 << 12)
  540. #define WM8350_DCDC_HIB_MODE_IMAGE (1 << 12)
  541. #define WM8350_DCDC_HIB_MODE_STANDBY (2 << 12)
  542. #define WM8350_DCDC_HIB_MODE_LDO (4 << 12)
  543. #define WM8350_DCDC_HIB_MODE_LDO_IM (5 << 12)
  544. #define WM8350_DCDC_HIB_MODE_DIS (7 << 12)
  545. #define WM8350_DCDC_HIB_MODE_MASK (7 << 12)
  546. /* DCDC Low Power (Hibernate) signal */
  547. #define WM8350_DCDC_HIB_SIG_REG (0 << 8)
  548. #define WM8350_DCDC_HIB_SIG_LPWR1 (1 << 8)
  549. #define WM8350_DCDC_HIB_SIG_LPWR2 (2 << 8)
  550. #define WM8350_DCDC_HIB_SIG_LPWR3 (3 << 8)
  551. /* LDO Low power (Hibernate) mode */
  552. #define WM8350_LDO_HIB_MODE_IMAGE (0 << 0)
  553. #define WM8350_LDO_HIB_MODE_DIS (1 << 0)
  554. /* LDO Low Power (Hibernate) signal */
  555. #define WM8350_LDO_HIB_SIG_REG (0 << 8)
  556. #define WM8350_LDO_HIB_SIG_LPWR1 (1 << 8)
  557. #define WM8350_LDO_HIB_SIG_LPWR2 (2 << 8)
  558. #define WM8350_LDO_HIB_SIG_LPWR3 (3 << 8)
  559. /*
  560. * LDOs
  561. */
  562. #define WM8350_LDO_1 6
  563. #define WM8350_LDO_2 7
  564. #define WM8350_LDO_3 8
  565. #define WM8350_LDO_4 9
  566. /*
  567. * ISINKs
  568. */
  569. #define WM8350_ISINK_A 10
  570. #define WM8350_ISINK_B 11
  571. #define WM8350_ISINK_MODE_BOOST 0
  572. #define WM8350_ISINK_MODE_SWITCH 1
  573. #define WM8350_ISINK_ILIM_NORMAL 0
  574. #define WM8350_ISINK_ILIM_LOW 1
  575. #define WM8350_ISINK_FLASH_DISABLE 0
  576. #define WM8350_ISINK_FLASH_ENABLE 1
  577. #define WM8350_ISINK_FLASH_TRIG_BIT 0
  578. #define WM8350_ISINK_FLASH_TRIG_GPIO 1
  579. #define WM8350_ISINK_FLASH_MODE_EN (1 << 13)
  580. #define WM8350_ISINK_FLASH_MODE_DIS (0 << 13)
  581. #define WM8350_ISINK_FLASH_DUR_32MS (0 << 8)
  582. #define WM8350_ISINK_FLASH_DUR_64MS (1 << 8)
  583. #define WM8350_ISINK_FLASH_DUR_96MS (2 << 8)
  584. #define WM8350_ISINK_FLASH_DUR_1024MS (3 << 8)
  585. #define WM8350_ISINK_FLASH_ON_INSTANT (0 << 0)
  586. #define WM8350_ISINK_FLASH_ON_0_25S (1 << 0)
  587. #define WM8350_ISINK_FLASH_ON_0_50S (2 << 0)
  588. #define WM8350_ISINK_FLASH_ON_1_00S (3 << 0)
  589. #define WM8350_ISINK_FLASH_ON_1_95S (1 << 0)
  590. #define WM8350_ISINK_FLASH_ON_3_91S (2 << 0)
  591. #define WM8350_ISINK_FLASH_ON_7_80S (3 << 0)
  592. #define WM8350_ISINK_FLASH_OFF_INSTANT (0 << 4)
  593. #define WM8350_ISINK_FLASH_OFF_0_25S (1 << 4)
  594. #define WM8350_ISINK_FLASH_OFF_0_50S (2 << 4)
  595. #define WM8350_ISINK_FLASH_OFF_1_00S (3 << 4)
  596. #define WM8350_ISINK_FLASH_OFF_1_95S (1 << 4)
  597. #define WM8350_ISINK_FLASH_OFF_3_91S (2 << 4)
  598. #define WM8350_ISINK_FLASH_OFF_7_80S (3 << 4)
  599. /*
  600. * Regulator Interrupts.
  601. */
  602. #define WM8350_IRQ_CS1 13
  603. #define WM8350_IRQ_CS2 14
  604. #define WM8350_IRQ_UV_LDO4 25
  605. #define WM8350_IRQ_UV_LDO3 26
  606. #define WM8350_IRQ_UV_LDO2 27
  607. #define WM8350_IRQ_UV_LDO1 28
  608. #define WM8350_IRQ_UV_DC6 29
  609. #define WM8350_IRQ_UV_DC5 30
  610. #define WM8350_IRQ_UV_DC4 31
  611. #define WM8350_IRQ_UV_DC3 32
  612. #define WM8350_IRQ_UV_DC2 33
  613. #define WM8350_IRQ_UV_DC1 34
  614. #define WM8350_IRQ_OC_LS 35
  615. #define NUM_WM8350_REGULATORS 12
  616. struct wm8350;
  617. struct platform_device;
  618. struct regulator_init_data;
  619. /*
  620. * WM8350 LED platform data
  621. */
  622. struct wm8350_led_platform_data {
  623. const char *name;
  624. const char *default_trigger;
  625. int max_uA;
  626. };
  627. struct wm8350_led {
  628. struct platform_device *pdev;
  629. struct work_struct work;
  630. spinlock_t value_lock;
  631. enum led_brightness value;
  632. struct led_classdev cdev;
  633. int max_uA_index;
  634. int enabled;
  635. struct regulator *isink;
  636. struct regulator_consumer_supply isink_consumer;
  637. struct regulator_init_data isink_init;
  638. struct regulator *dcdc;
  639. struct regulator_consumer_supply dcdc_consumer;
  640. struct regulator_init_data dcdc_init;
  641. };
  642. struct wm8350_pmic {
  643. /* Number of regulators of each type on this device */
  644. int max_dcdc;
  645. int max_isink;
  646. /* ISINK to DCDC mapping */
  647. int isink_A_dcdc;
  648. int isink_B_dcdc;
  649. /* hibernate configs */
  650. u16 dcdc1_hib_mode;
  651. u16 dcdc3_hib_mode;
  652. u16 dcdc4_hib_mode;
  653. u16 dcdc6_hib_mode;
  654. /* regulator devices */
  655. struct platform_device *pdev[NUM_WM8350_REGULATORS];
  656. /* LED devices */
  657. struct wm8350_led led[2];
  658. };
  659. int wm8350_register_regulator(struct wm8350 *wm8350, int reg,
  660. struct regulator_init_data *initdata);
  661. int wm8350_register_led(struct wm8350 *wm8350, int lednum, int dcdc, int isink,
  662. struct wm8350_led_platform_data *pdata);
  663. /*
  664. * Additional DCDC control not supported via regulator API
  665. */
  666. int wm8350_dcdc_set_slot(struct wm8350 *wm8350, int dcdc, u16 start,
  667. u16 stop, u16 fault);
  668. int wm8350_dcdc25_set_mode(struct wm8350 *wm8350, int dcdc, u16 mode,
  669. u16 ilim, u16 ramp, u16 feedback);
  670. /*
  671. * Additional LDO control not supported via regulator API
  672. */
  673. int wm8350_ldo_set_slot(struct wm8350 *wm8350, int ldo, u16 start, u16 stop);
  674. /*
  675. * Additional ISINK control not supported via regulator API
  676. */
  677. int wm8350_isink_set_flash(struct wm8350 *wm8350, int isink, u16 mode,
  678. u16 trigger, u16 duration, u16 on_ramp,
  679. u16 off_ramp, u16 drive);
  680. #endif