qla_isr.c 90 KB

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  1. /*
  2. * QLogic Fibre Channel HBA Driver
  3. * Copyright (c) 2003-2014 QLogic Corporation
  4. *
  5. * See LICENSE.qla2xxx for copyright and licensing details.
  6. */
  7. #include "qla_def.h"
  8. #include "qla_target.h"
  9. #include <linux/delay.h>
  10. #include <linux/slab.h>
  11. #include <scsi/scsi_tcq.h>
  12. #include <scsi/scsi_bsg_fc.h>
  13. #include <scsi/scsi_eh.h>
  14. static void qla2x00_mbx_completion(scsi_qla_host_t *, uint16_t);
  15. static void qla2x00_status_entry(scsi_qla_host_t *, struct rsp_que *, void *);
  16. static void qla2x00_status_cont_entry(struct rsp_que *, sts_cont_entry_t *);
  17. static void qla2x00_error_entry(scsi_qla_host_t *, struct rsp_que *,
  18. sts_entry_t *);
  19. static void qla_irq_affinity_notify(struct irq_affinity_notify *,
  20. const cpumask_t *);
  21. static void qla_irq_affinity_release(struct kref *);
  22. /**
  23. * qla2100_intr_handler() - Process interrupts for the ISP2100 and ISP2200.
  24. * @irq:
  25. * @dev_id: SCSI driver HA context
  26. *
  27. * Called by system whenever the host adapter generates an interrupt.
  28. *
  29. * Returns handled flag.
  30. */
  31. irqreturn_t
  32. qla2100_intr_handler(int irq, void *dev_id)
  33. {
  34. scsi_qla_host_t *vha;
  35. struct qla_hw_data *ha;
  36. struct device_reg_2xxx __iomem *reg;
  37. int status;
  38. unsigned long iter;
  39. uint16_t hccr;
  40. uint16_t mb[4];
  41. struct rsp_que *rsp;
  42. unsigned long flags;
  43. rsp = (struct rsp_que *) dev_id;
  44. if (!rsp) {
  45. ql_log(ql_log_info, NULL, 0x505d,
  46. "%s: NULL response queue pointer.\n", __func__);
  47. return (IRQ_NONE);
  48. }
  49. ha = rsp->hw;
  50. reg = &ha->iobase->isp;
  51. status = 0;
  52. spin_lock_irqsave(&ha->hardware_lock, flags);
  53. vha = pci_get_drvdata(ha->pdev);
  54. for (iter = 50; iter--; ) {
  55. hccr = RD_REG_WORD(&reg->hccr);
  56. if (qla2x00_check_reg16_for_disconnect(vha, hccr))
  57. break;
  58. if (hccr & HCCR_RISC_PAUSE) {
  59. if (pci_channel_offline(ha->pdev))
  60. break;
  61. /*
  62. * Issue a "HARD" reset in order for the RISC interrupt
  63. * bit to be cleared. Schedule a big hammer to get
  64. * out of the RISC PAUSED state.
  65. */
  66. WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
  67. RD_REG_WORD(&reg->hccr);
  68. ha->isp_ops->fw_dump(vha, 1);
  69. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  70. break;
  71. } else if ((RD_REG_WORD(&reg->istatus) & ISR_RISC_INT) == 0)
  72. break;
  73. if (RD_REG_WORD(&reg->semaphore) & BIT_0) {
  74. WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
  75. RD_REG_WORD(&reg->hccr);
  76. /* Get mailbox data. */
  77. mb[0] = RD_MAILBOX_REG(ha, reg, 0);
  78. if (mb[0] > 0x3fff && mb[0] < 0x8000) {
  79. qla2x00_mbx_completion(vha, mb[0]);
  80. status |= MBX_INTERRUPT;
  81. } else if (mb[0] > 0x7fff && mb[0] < 0xc000) {
  82. mb[1] = RD_MAILBOX_REG(ha, reg, 1);
  83. mb[2] = RD_MAILBOX_REG(ha, reg, 2);
  84. mb[3] = RD_MAILBOX_REG(ha, reg, 3);
  85. qla2x00_async_event(vha, rsp, mb);
  86. } else {
  87. /*EMPTY*/
  88. ql_dbg(ql_dbg_async, vha, 0x5025,
  89. "Unrecognized interrupt type (%d).\n",
  90. mb[0]);
  91. }
  92. /* Release mailbox registers. */
  93. WRT_REG_WORD(&reg->semaphore, 0);
  94. RD_REG_WORD(&reg->semaphore);
  95. } else {
  96. qla2x00_process_response_queue(rsp);
  97. WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
  98. RD_REG_WORD(&reg->hccr);
  99. }
  100. }
  101. qla2x00_handle_mbx_completion(ha, status);
  102. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  103. return (IRQ_HANDLED);
  104. }
  105. bool
  106. qla2x00_check_reg32_for_disconnect(scsi_qla_host_t *vha, uint32_t reg)
  107. {
  108. /* Check for PCI disconnection */
  109. if (reg == 0xffffffff && !pci_channel_offline(vha->hw->pdev)) {
  110. if (!test_and_set_bit(PFLG_DISCONNECTED, &vha->pci_flags) &&
  111. !test_bit(PFLG_DRIVER_REMOVING, &vha->pci_flags) &&
  112. !test_bit(PFLG_DRIVER_PROBING, &vha->pci_flags)) {
  113. /*
  114. * Schedule this (only once) on the default system
  115. * workqueue so that all the adapter workqueues and the
  116. * DPC thread can be shutdown cleanly.
  117. */
  118. schedule_work(&vha->hw->board_disable);
  119. }
  120. return true;
  121. } else
  122. return false;
  123. }
  124. bool
  125. qla2x00_check_reg16_for_disconnect(scsi_qla_host_t *vha, uint16_t reg)
  126. {
  127. return qla2x00_check_reg32_for_disconnect(vha, 0xffff0000 | reg);
  128. }
  129. /**
  130. * qla2300_intr_handler() - Process interrupts for the ISP23xx and ISP63xx.
  131. * @irq:
  132. * @dev_id: SCSI driver HA context
  133. *
  134. * Called by system whenever the host adapter generates an interrupt.
  135. *
  136. * Returns handled flag.
  137. */
  138. irqreturn_t
  139. qla2300_intr_handler(int irq, void *dev_id)
  140. {
  141. scsi_qla_host_t *vha;
  142. struct device_reg_2xxx __iomem *reg;
  143. int status;
  144. unsigned long iter;
  145. uint32_t stat;
  146. uint16_t hccr;
  147. uint16_t mb[4];
  148. struct rsp_que *rsp;
  149. struct qla_hw_data *ha;
  150. unsigned long flags;
  151. rsp = (struct rsp_que *) dev_id;
  152. if (!rsp) {
  153. ql_log(ql_log_info, NULL, 0x5058,
  154. "%s: NULL response queue pointer.\n", __func__);
  155. return (IRQ_NONE);
  156. }
  157. ha = rsp->hw;
  158. reg = &ha->iobase->isp;
  159. status = 0;
  160. spin_lock_irqsave(&ha->hardware_lock, flags);
  161. vha = pci_get_drvdata(ha->pdev);
  162. for (iter = 50; iter--; ) {
  163. stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
  164. if (qla2x00_check_reg32_for_disconnect(vha, stat))
  165. break;
  166. if (stat & HSR_RISC_PAUSED) {
  167. if (unlikely(pci_channel_offline(ha->pdev)))
  168. break;
  169. hccr = RD_REG_WORD(&reg->hccr);
  170. if (hccr & (BIT_15 | BIT_13 | BIT_11 | BIT_8))
  171. ql_log(ql_log_warn, vha, 0x5026,
  172. "Parity error -- HCCR=%x, Dumping "
  173. "firmware.\n", hccr);
  174. else
  175. ql_log(ql_log_warn, vha, 0x5027,
  176. "RISC paused -- HCCR=%x, Dumping "
  177. "firmware.\n", hccr);
  178. /*
  179. * Issue a "HARD" reset in order for the RISC
  180. * interrupt bit to be cleared. Schedule a big
  181. * hammer to get out of the RISC PAUSED state.
  182. */
  183. WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
  184. RD_REG_WORD(&reg->hccr);
  185. ha->isp_ops->fw_dump(vha, 1);
  186. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  187. break;
  188. } else if ((stat & HSR_RISC_INT) == 0)
  189. break;
  190. switch (stat & 0xff) {
  191. case 0x1:
  192. case 0x2:
  193. case 0x10:
  194. case 0x11:
  195. qla2x00_mbx_completion(vha, MSW(stat));
  196. status |= MBX_INTERRUPT;
  197. /* Release mailbox registers. */
  198. WRT_REG_WORD(&reg->semaphore, 0);
  199. break;
  200. case 0x12:
  201. mb[0] = MSW(stat);
  202. mb[1] = RD_MAILBOX_REG(ha, reg, 1);
  203. mb[2] = RD_MAILBOX_REG(ha, reg, 2);
  204. mb[3] = RD_MAILBOX_REG(ha, reg, 3);
  205. qla2x00_async_event(vha, rsp, mb);
  206. break;
  207. case 0x13:
  208. qla2x00_process_response_queue(rsp);
  209. break;
  210. case 0x15:
  211. mb[0] = MBA_CMPLT_1_16BIT;
  212. mb[1] = MSW(stat);
  213. qla2x00_async_event(vha, rsp, mb);
  214. break;
  215. case 0x16:
  216. mb[0] = MBA_SCSI_COMPLETION;
  217. mb[1] = MSW(stat);
  218. mb[2] = RD_MAILBOX_REG(ha, reg, 2);
  219. qla2x00_async_event(vha, rsp, mb);
  220. break;
  221. default:
  222. ql_dbg(ql_dbg_async, vha, 0x5028,
  223. "Unrecognized interrupt type (%d).\n", stat & 0xff);
  224. break;
  225. }
  226. WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
  227. RD_REG_WORD_RELAXED(&reg->hccr);
  228. }
  229. qla2x00_handle_mbx_completion(ha, status);
  230. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  231. return (IRQ_HANDLED);
  232. }
  233. /**
  234. * qla2x00_mbx_completion() - Process mailbox command completions.
  235. * @ha: SCSI driver HA context
  236. * @mb0: Mailbox0 register
  237. */
  238. static void
  239. qla2x00_mbx_completion(scsi_qla_host_t *vha, uint16_t mb0)
  240. {
  241. uint16_t cnt;
  242. uint32_t mboxes;
  243. uint16_t __iomem *wptr;
  244. struct qla_hw_data *ha = vha->hw;
  245. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  246. /* Read all mbox registers? */
  247. mboxes = (1 << ha->mbx_count) - 1;
  248. if (!ha->mcp)
  249. ql_dbg(ql_dbg_async, vha, 0x5001, "MBX pointer ERROR.\n");
  250. else
  251. mboxes = ha->mcp->in_mb;
  252. /* Load return mailbox registers. */
  253. ha->flags.mbox_int = 1;
  254. ha->mailbox_out[0] = mb0;
  255. mboxes >>= 1;
  256. wptr = (uint16_t __iomem *)MAILBOX_REG(ha, reg, 1);
  257. for (cnt = 1; cnt < ha->mbx_count; cnt++) {
  258. if (IS_QLA2200(ha) && cnt == 8)
  259. wptr = (uint16_t __iomem *)MAILBOX_REG(ha, reg, 8);
  260. if ((cnt == 4 || cnt == 5) && (mboxes & BIT_0))
  261. ha->mailbox_out[cnt] = qla2x00_debounce_register(wptr);
  262. else if (mboxes & BIT_0)
  263. ha->mailbox_out[cnt] = RD_REG_WORD(wptr);
  264. wptr++;
  265. mboxes >>= 1;
  266. }
  267. }
  268. static void
  269. qla81xx_idc_event(scsi_qla_host_t *vha, uint16_t aen, uint16_t descr)
  270. {
  271. static char *event[] =
  272. { "Complete", "Request Notification", "Time Extension" };
  273. int rval;
  274. struct device_reg_24xx __iomem *reg24 = &vha->hw->iobase->isp24;
  275. struct device_reg_82xx __iomem *reg82 = &vha->hw->iobase->isp82;
  276. uint16_t __iomem *wptr;
  277. uint16_t cnt, timeout, mb[QLA_IDC_ACK_REGS];
  278. /* Seed data -- mailbox1 -> mailbox7. */
  279. if (IS_QLA81XX(vha->hw) || IS_QLA83XX(vha->hw))
  280. wptr = (uint16_t __iomem *)&reg24->mailbox1;
  281. else if (IS_QLA8044(vha->hw))
  282. wptr = (uint16_t __iomem *)&reg82->mailbox_out[1];
  283. else
  284. return;
  285. for (cnt = 0; cnt < QLA_IDC_ACK_REGS; cnt++, wptr++)
  286. mb[cnt] = RD_REG_WORD(wptr);
  287. ql_dbg(ql_dbg_async, vha, 0x5021,
  288. "Inter-Driver Communication %s -- "
  289. "%04x %04x %04x %04x %04x %04x %04x.\n",
  290. event[aen & 0xff], mb[0], mb[1], mb[2], mb[3],
  291. mb[4], mb[5], mb[6]);
  292. switch (aen) {
  293. /* Handle IDC Error completion case. */
  294. case MBA_IDC_COMPLETE:
  295. if (mb[1] >> 15) {
  296. vha->hw->flags.idc_compl_status = 1;
  297. if (vha->hw->notify_dcbx_comp && !vha->vp_idx)
  298. complete(&vha->hw->dcbx_comp);
  299. }
  300. break;
  301. case MBA_IDC_NOTIFY:
  302. /* Acknowledgement needed? [Notify && non-zero timeout]. */
  303. timeout = (descr >> 8) & 0xf;
  304. ql_dbg(ql_dbg_async, vha, 0x5022,
  305. "%lu Inter-Driver Communication %s -- ACK timeout=%d.\n",
  306. vha->host_no, event[aen & 0xff], timeout);
  307. if (!timeout)
  308. return;
  309. rval = qla2x00_post_idc_ack_work(vha, mb);
  310. if (rval != QLA_SUCCESS)
  311. ql_log(ql_log_warn, vha, 0x5023,
  312. "IDC failed to post ACK.\n");
  313. break;
  314. case MBA_IDC_TIME_EXT:
  315. vha->hw->idc_extend_tmo = descr;
  316. ql_dbg(ql_dbg_async, vha, 0x5087,
  317. "%lu Inter-Driver Communication %s -- "
  318. "Extend timeout by=%d.\n",
  319. vha->host_no, event[aen & 0xff], vha->hw->idc_extend_tmo);
  320. break;
  321. }
  322. }
  323. #define LS_UNKNOWN 2
  324. const char *
  325. qla2x00_get_link_speed_str(struct qla_hw_data *ha, uint16_t speed)
  326. {
  327. static const char *const link_speeds[] = {
  328. "1", "2", "?", "4", "8", "16", "32", "10"
  329. };
  330. #define QLA_LAST_SPEED 7
  331. if (IS_QLA2100(ha) || IS_QLA2200(ha))
  332. return link_speeds[0];
  333. else if (speed == 0x13)
  334. return link_speeds[QLA_LAST_SPEED];
  335. else if (speed < QLA_LAST_SPEED)
  336. return link_speeds[speed];
  337. else
  338. return link_speeds[LS_UNKNOWN];
  339. }
  340. static void
  341. qla83xx_handle_8200_aen(scsi_qla_host_t *vha, uint16_t *mb)
  342. {
  343. struct qla_hw_data *ha = vha->hw;
  344. /*
  345. * 8200 AEN Interpretation:
  346. * mb[0] = AEN code
  347. * mb[1] = AEN Reason code
  348. * mb[2] = LSW of Peg-Halt Status-1 Register
  349. * mb[6] = MSW of Peg-Halt Status-1 Register
  350. * mb[3] = LSW of Peg-Halt Status-2 register
  351. * mb[7] = MSW of Peg-Halt Status-2 register
  352. * mb[4] = IDC Device-State Register value
  353. * mb[5] = IDC Driver-Presence Register value
  354. */
  355. ql_dbg(ql_dbg_async, vha, 0x506b, "AEN Code: mb[0] = 0x%x AEN reason: "
  356. "mb[1] = 0x%x PH-status1: mb[2] = 0x%x PH-status1: mb[6] = 0x%x.\n",
  357. mb[0], mb[1], mb[2], mb[6]);
  358. ql_dbg(ql_dbg_async, vha, 0x506c, "PH-status2: mb[3] = 0x%x "
  359. "PH-status2: mb[7] = 0x%x Device-State: mb[4] = 0x%x "
  360. "Drv-Presence: mb[5] = 0x%x.\n", mb[3], mb[7], mb[4], mb[5]);
  361. if (mb[1] & (IDC_PEG_HALT_STATUS_CHANGE | IDC_NIC_FW_REPORTED_FAILURE |
  362. IDC_HEARTBEAT_FAILURE)) {
  363. ha->flags.nic_core_hung = 1;
  364. ql_log(ql_log_warn, vha, 0x5060,
  365. "83XX: F/W Error Reported: Check if reset required.\n");
  366. if (mb[1] & IDC_PEG_HALT_STATUS_CHANGE) {
  367. uint32_t protocol_engine_id, fw_err_code, err_level;
  368. /*
  369. * IDC_PEG_HALT_STATUS_CHANGE interpretation:
  370. * - PEG-Halt Status-1 Register:
  371. * (LSW = mb[2], MSW = mb[6])
  372. * Bits 0-7 = protocol-engine ID
  373. * Bits 8-28 = f/w error code
  374. * Bits 29-31 = Error-level
  375. * Error-level 0x1 = Non-Fatal error
  376. * Error-level 0x2 = Recoverable Fatal error
  377. * Error-level 0x4 = UnRecoverable Fatal error
  378. * - PEG-Halt Status-2 Register:
  379. * (LSW = mb[3], MSW = mb[7])
  380. */
  381. protocol_engine_id = (mb[2] & 0xff);
  382. fw_err_code = (((mb[2] & 0xff00) >> 8) |
  383. ((mb[6] & 0x1fff) << 8));
  384. err_level = ((mb[6] & 0xe000) >> 13);
  385. ql_log(ql_log_warn, vha, 0x5061, "PegHalt Status-1 "
  386. "Register: protocol_engine_id=0x%x "
  387. "fw_err_code=0x%x err_level=0x%x.\n",
  388. protocol_engine_id, fw_err_code, err_level);
  389. ql_log(ql_log_warn, vha, 0x5062, "PegHalt Status-2 "
  390. "Register: 0x%x%x.\n", mb[7], mb[3]);
  391. if (err_level == ERR_LEVEL_NON_FATAL) {
  392. ql_log(ql_log_warn, vha, 0x5063,
  393. "Not a fatal error, f/w has recovered "
  394. "iteself.\n");
  395. } else if (err_level == ERR_LEVEL_RECOVERABLE_FATAL) {
  396. ql_log(ql_log_fatal, vha, 0x5064,
  397. "Recoverable Fatal error: Chip reset "
  398. "required.\n");
  399. qla83xx_schedule_work(vha,
  400. QLA83XX_NIC_CORE_RESET);
  401. } else if (err_level == ERR_LEVEL_UNRECOVERABLE_FATAL) {
  402. ql_log(ql_log_fatal, vha, 0x5065,
  403. "Unrecoverable Fatal error: Set FAILED "
  404. "state, reboot required.\n");
  405. qla83xx_schedule_work(vha,
  406. QLA83XX_NIC_CORE_UNRECOVERABLE);
  407. }
  408. }
  409. if (mb[1] & IDC_NIC_FW_REPORTED_FAILURE) {
  410. uint16_t peg_fw_state, nw_interface_link_up;
  411. uint16_t nw_interface_signal_detect, sfp_status;
  412. uint16_t htbt_counter, htbt_monitor_enable;
  413. uint16_t sfp_additonal_info, sfp_multirate;
  414. uint16_t sfp_tx_fault, link_speed, dcbx_status;
  415. /*
  416. * IDC_NIC_FW_REPORTED_FAILURE interpretation:
  417. * - PEG-to-FC Status Register:
  418. * (LSW = mb[2], MSW = mb[6])
  419. * Bits 0-7 = Peg-Firmware state
  420. * Bit 8 = N/W Interface Link-up
  421. * Bit 9 = N/W Interface signal detected
  422. * Bits 10-11 = SFP Status
  423. * SFP Status 0x0 = SFP+ transceiver not expected
  424. * SFP Status 0x1 = SFP+ transceiver not present
  425. * SFP Status 0x2 = SFP+ transceiver invalid
  426. * SFP Status 0x3 = SFP+ transceiver present and
  427. * valid
  428. * Bits 12-14 = Heartbeat Counter
  429. * Bit 15 = Heartbeat Monitor Enable
  430. * Bits 16-17 = SFP Additional Info
  431. * SFP info 0x0 = Unregocnized transceiver for
  432. * Ethernet
  433. * SFP info 0x1 = SFP+ brand validation failed
  434. * SFP info 0x2 = SFP+ speed validation failed
  435. * SFP info 0x3 = SFP+ access error
  436. * Bit 18 = SFP Multirate
  437. * Bit 19 = SFP Tx Fault
  438. * Bits 20-22 = Link Speed
  439. * Bits 23-27 = Reserved
  440. * Bits 28-30 = DCBX Status
  441. * DCBX Status 0x0 = DCBX Disabled
  442. * DCBX Status 0x1 = DCBX Enabled
  443. * DCBX Status 0x2 = DCBX Exchange error
  444. * Bit 31 = Reserved
  445. */
  446. peg_fw_state = (mb[2] & 0x00ff);
  447. nw_interface_link_up = ((mb[2] & 0x0100) >> 8);
  448. nw_interface_signal_detect = ((mb[2] & 0x0200) >> 9);
  449. sfp_status = ((mb[2] & 0x0c00) >> 10);
  450. htbt_counter = ((mb[2] & 0x7000) >> 12);
  451. htbt_monitor_enable = ((mb[2] & 0x8000) >> 15);
  452. sfp_additonal_info = (mb[6] & 0x0003);
  453. sfp_multirate = ((mb[6] & 0x0004) >> 2);
  454. sfp_tx_fault = ((mb[6] & 0x0008) >> 3);
  455. link_speed = ((mb[6] & 0x0070) >> 4);
  456. dcbx_status = ((mb[6] & 0x7000) >> 12);
  457. ql_log(ql_log_warn, vha, 0x5066,
  458. "Peg-to-Fc Status Register:\n"
  459. "peg_fw_state=0x%x, nw_interface_link_up=0x%x, "
  460. "nw_interface_signal_detect=0x%x"
  461. "\nsfp_statis=0x%x.\n ", peg_fw_state,
  462. nw_interface_link_up, nw_interface_signal_detect,
  463. sfp_status);
  464. ql_log(ql_log_warn, vha, 0x5067,
  465. "htbt_counter=0x%x, htbt_monitor_enable=0x%x, "
  466. "sfp_additonal_info=0x%x, sfp_multirate=0x%x.\n ",
  467. htbt_counter, htbt_monitor_enable,
  468. sfp_additonal_info, sfp_multirate);
  469. ql_log(ql_log_warn, vha, 0x5068,
  470. "sfp_tx_fault=0x%x, link_state=0x%x, "
  471. "dcbx_status=0x%x.\n", sfp_tx_fault, link_speed,
  472. dcbx_status);
  473. qla83xx_schedule_work(vha, QLA83XX_NIC_CORE_RESET);
  474. }
  475. if (mb[1] & IDC_HEARTBEAT_FAILURE) {
  476. ql_log(ql_log_warn, vha, 0x5069,
  477. "Heartbeat Failure encountered, chip reset "
  478. "required.\n");
  479. qla83xx_schedule_work(vha, QLA83XX_NIC_CORE_RESET);
  480. }
  481. }
  482. if (mb[1] & IDC_DEVICE_STATE_CHANGE) {
  483. ql_log(ql_log_info, vha, 0x506a,
  484. "IDC Device-State changed = 0x%x.\n", mb[4]);
  485. if (ha->flags.nic_core_reset_owner)
  486. return;
  487. qla83xx_schedule_work(vha, MBA_IDC_AEN);
  488. }
  489. }
  490. int
  491. qla2x00_is_a_vp_did(scsi_qla_host_t *vha, uint32_t rscn_entry)
  492. {
  493. struct qla_hw_data *ha = vha->hw;
  494. scsi_qla_host_t *vp;
  495. uint32_t vp_did;
  496. unsigned long flags;
  497. int ret = 0;
  498. if (!ha->num_vhosts)
  499. return ret;
  500. spin_lock_irqsave(&ha->vport_slock, flags);
  501. list_for_each_entry(vp, &ha->vp_list, list) {
  502. vp_did = vp->d_id.b24;
  503. if (vp_did == rscn_entry) {
  504. ret = 1;
  505. break;
  506. }
  507. }
  508. spin_unlock_irqrestore(&ha->vport_slock, flags);
  509. return ret;
  510. }
  511. static inline fc_port_t *
  512. qla2x00_find_fcport_by_loopid(scsi_qla_host_t *vha, uint16_t loop_id)
  513. {
  514. fc_port_t *fcport;
  515. list_for_each_entry(fcport, &vha->vp_fcports, list)
  516. if (fcport->loop_id == loop_id)
  517. return fcport;
  518. return NULL;
  519. }
  520. /**
  521. * qla2x00_async_event() - Process aynchronous events.
  522. * @ha: SCSI driver HA context
  523. * @mb: Mailbox registers (0 - 3)
  524. */
  525. void
  526. qla2x00_async_event(scsi_qla_host_t *vha, struct rsp_que *rsp, uint16_t *mb)
  527. {
  528. uint16_t handle_cnt;
  529. uint16_t cnt, mbx;
  530. uint32_t handles[5];
  531. struct qla_hw_data *ha = vha->hw;
  532. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  533. struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
  534. struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82;
  535. uint32_t rscn_entry, host_pid;
  536. unsigned long flags;
  537. fc_port_t *fcport = NULL;
  538. /* Setup to process RIO completion. */
  539. handle_cnt = 0;
  540. if (IS_CNA_CAPABLE(ha))
  541. goto skip_rio;
  542. switch (mb[0]) {
  543. case MBA_SCSI_COMPLETION:
  544. handles[0] = le32_to_cpu((uint32_t)((mb[2] << 16) | mb[1]));
  545. handle_cnt = 1;
  546. break;
  547. case MBA_CMPLT_1_16BIT:
  548. handles[0] = mb[1];
  549. handle_cnt = 1;
  550. mb[0] = MBA_SCSI_COMPLETION;
  551. break;
  552. case MBA_CMPLT_2_16BIT:
  553. handles[0] = mb[1];
  554. handles[1] = mb[2];
  555. handle_cnt = 2;
  556. mb[0] = MBA_SCSI_COMPLETION;
  557. break;
  558. case MBA_CMPLT_3_16BIT:
  559. handles[0] = mb[1];
  560. handles[1] = mb[2];
  561. handles[2] = mb[3];
  562. handle_cnt = 3;
  563. mb[0] = MBA_SCSI_COMPLETION;
  564. break;
  565. case MBA_CMPLT_4_16BIT:
  566. handles[0] = mb[1];
  567. handles[1] = mb[2];
  568. handles[2] = mb[3];
  569. handles[3] = (uint32_t)RD_MAILBOX_REG(ha, reg, 6);
  570. handle_cnt = 4;
  571. mb[0] = MBA_SCSI_COMPLETION;
  572. break;
  573. case MBA_CMPLT_5_16BIT:
  574. handles[0] = mb[1];
  575. handles[1] = mb[2];
  576. handles[2] = mb[3];
  577. handles[3] = (uint32_t)RD_MAILBOX_REG(ha, reg, 6);
  578. handles[4] = (uint32_t)RD_MAILBOX_REG(ha, reg, 7);
  579. handle_cnt = 5;
  580. mb[0] = MBA_SCSI_COMPLETION;
  581. break;
  582. case MBA_CMPLT_2_32BIT:
  583. handles[0] = le32_to_cpu((uint32_t)((mb[2] << 16) | mb[1]));
  584. handles[1] = le32_to_cpu(
  585. ((uint32_t)(RD_MAILBOX_REG(ha, reg, 7) << 16)) |
  586. RD_MAILBOX_REG(ha, reg, 6));
  587. handle_cnt = 2;
  588. mb[0] = MBA_SCSI_COMPLETION;
  589. break;
  590. default:
  591. break;
  592. }
  593. skip_rio:
  594. switch (mb[0]) {
  595. case MBA_SCSI_COMPLETION: /* Fast Post */
  596. if (!vha->flags.online)
  597. break;
  598. for (cnt = 0; cnt < handle_cnt; cnt++)
  599. qla2x00_process_completed_request(vha, rsp->req,
  600. handles[cnt]);
  601. break;
  602. case MBA_RESET: /* Reset */
  603. ql_dbg(ql_dbg_async, vha, 0x5002,
  604. "Asynchronous RESET.\n");
  605. set_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
  606. break;
  607. case MBA_SYSTEM_ERR: /* System Error */
  608. mbx = (IS_QLA81XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha)) ?
  609. RD_REG_WORD(&reg24->mailbox7) : 0;
  610. ql_log(ql_log_warn, vha, 0x5003,
  611. "ISP System Error - mbx1=%xh mbx2=%xh mbx3=%xh "
  612. "mbx7=%xh.\n", mb[1], mb[2], mb[3], mbx);
  613. ha->isp_ops->fw_dump(vha, 1);
  614. if (IS_FWI2_CAPABLE(ha)) {
  615. if (mb[1] == 0 && mb[2] == 0) {
  616. ql_log(ql_log_fatal, vha, 0x5004,
  617. "Unrecoverable Hardware Error: adapter "
  618. "marked OFFLINE!\n");
  619. vha->flags.online = 0;
  620. vha->device_flags |= DFLG_DEV_FAILED;
  621. } else {
  622. /* Check to see if MPI timeout occurred */
  623. if ((mbx & MBX_3) && (ha->port_no == 0))
  624. set_bit(MPI_RESET_NEEDED,
  625. &vha->dpc_flags);
  626. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  627. }
  628. } else if (mb[1] == 0) {
  629. ql_log(ql_log_fatal, vha, 0x5005,
  630. "Unrecoverable Hardware Error: adapter marked "
  631. "OFFLINE!\n");
  632. vha->flags.online = 0;
  633. vha->device_flags |= DFLG_DEV_FAILED;
  634. } else
  635. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  636. break;
  637. case MBA_REQ_TRANSFER_ERR: /* Request Transfer Error */
  638. ql_log(ql_log_warn, vha, 0x5006,
  639. "ISP Request Transfer Error (%x).\n", mb[1]);
  640. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  641. break;
  642. case MBA_RSP_TRANSFER_ERR: /* Response Transfer Error */
  643. ql_log(ql_log_warn, vha, 0x5007,
  644. "ISP Response Transfer Error (%x).\n", mb[1]);
  645. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  646. break;
  647. case MBA_WAKEUP_THRES: /* Request Queue Wake-up */
  648. ql_dbg(ql_dbg_async, vha, 0x5008,
  649. "Asynchronous WAKEUP_THRES (%x).\n", mb[1]);
  650. break;
  651. case MBA_LOOP_INIT_ERR:
  652. ql_log(ql_log_warn, vha, 0x5090,
  653. "LOOP INIT ERROR (%x).\n", mb[1]);
  654. ha->isp_ops->fw_dump(vha, 1);
  655. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  656. break;
  657. case MBA_LIP_OCCURRED: /* Loop Initialization Procedure */
  658. ql_dbg(ql_dbg_async, vha, 0x5009,
  659. "LIP occurred (%x).\n", mb[1]);
  660. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  661. atomic_set(&vha->loop_state, LOOP_DOWN);
  662. atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
  663. qla2x00_mark_all_devices_lost(vha, 1);
  664. }
  665. if (vha->vp_idx) {
  666. atomic_set(&vha->vp_state, VP_FAILED);
  667. fc_vport_set_state(vha->fc_vport, FC_VPORT_FAILED);
  668. }
  669. set_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags);
  670. set_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags);
  671. vha->flags.management_server_logged_in = 0;
  672. qla2x00_post_aen_work(vha, FCH_EVT_LIP, mb[1]);
  673. break;
  674. case MBA_LOOP_UP: /* Loop Up Event */
  675. if (IS_QLA2100(ha) || IS_QLA2200(ha))
  676. ha->link_data_rate = PORT_SPEED_1GB;
  677. else
  678. ha->link_data_rate = mb[1];
  679. ql_log(ql_log_info, vha, 0x500a,
  680. "LOOP UP detected (%s Gbps).\n",
  681. qla2x00_get_link_speed_str(ha, ha->link_data_rate));
  682. vha->flags.management_server_logged_in = 0;
  683. qla2x00_post_aen_work(vha, FCH_EVT_LINKUP, ha->link_data_rate);
  684. break;
  685. case MBA_LOOP_DOWN: /* Loop Down Event */
  686. mbx = (IS_QLA81XX(ha) || IS_QLA8031(ha))
  687. ? RD_REG_WORD(&reg24->mailbox4) : 0;
  688. mbx = (IS_P3P_TYPE(ha)) ? RD_REG_WORD(&reg82->mailbox_out[4])
  689. : mbx;
  690. ql_log(ql_log_info, vha, 0x500b,
  691. "LOOP DOWN detected (%x %x %x %x).\n",
  692. mb[1], mb[2], mb[3], mbx);
  693. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  694. atomic_set(&vha->loop_state, LOOP_DOWN);
  695. atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
  696. /*
  697. * In case of loop down, restore WWPN from
  698. * NVRAM in case of FA-WWPN capable ISP
  699. * Restore for Physical Port only
  700. */
  701. if (!vha->vp_idx) {
  702. if (ha->flags.fawwpn_enabled) {
  703. void *wwpn = ha->init_cb->port_name;
  704. memcpy(vha->port_name, wwpn, WWN_SIZE);
  705. fc_host_port_name(vha->host) =
  706. wwn_to_u64(vha->port_name);
  707. ql_dbg(ql_dbg_init + ql_dbg_verbose,
  708. vha, 0x0144, "LOOP DOWN detected,"
  709. "restore WWPN %016llx\n",
  710. wwn_to_u64(vha->port_name));
  711. }
  712. clear_bit(VP_CONFIG_OK, &vha->vp_flags);
  713. }
  714. vha->device_flags |= DFLG_NO_CABLE;
  715. qla2x00_mark_all_devices_lost(vha, 1);
  716. }
  717. if (vha->vp_idx) {
  718. atomic_set(&vha->vp_state, VP_FAILED);
  719. fc_vport_set_state(vha->fc_vport, FC_VPORT_FAILED);
  720. }
  721. vha->flags.management_server_logged_in = 0;
  722. ha->link_data_rate = PORT_SPEED_UNKNOWN;
  723. qla2x00_post_aen_work(vha, FCH_EVT_LINKDOWN, 0);
  724. break;
  725. case MBA_LIP_RESET: /* LIP reset occurred */
  726. ql_dbg(ql_dbg_async, vha, 0x500c,
  727. "LIP reset occurred (%x).\n", mb[1]);
  728. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  729. atomic_set(&vha->loop_state, LOOP_DOWN);
  730. atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
  731. qla2x00_mark_all_devices_lost(vha, 1);
  732. }
  733. if (vha->vp_idx) {
  734. atomic_set(&vha->vp_state, VP_FAILED);
  735. fc_vport_set_state(vha->fc_vport, FC_VPORT_FAILED);
  736. }
  737. set_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
  738. ha->operating_mode = LOOP;
  739. vha->flags.management_server_logged_in = 0;
  740. qla2x00_post_aen_work(vha, FCH_EVT_LIPRESET, mb[1]);
  741. break;
  742. /* case MBA_DCBX_COMPLETE: */
  743. case MBA_POINT_TO_POINT: /* Point-to-Point */
  744. if (IS_QLA2100(ha))
  745. break;
  746. if (IS_CNA_CAPABLE(ha)) {
  747. ql_dbg(ql_dbg_async, vha, 0x500d,
  748. "DCBX Completed -- %04x %04x %04x.\n",
  749. mb[1], mb[2], mb[3]);
  750. if (ha->notify_dcbx_comp && !vha->vp_idx)
  751. complete(&ha->dcbx_comp);
  752. } else
  753. ql_dbg(ql_dbg_async, vha, 0x500e,
  754. "Asynchronous P2P MODE received.\n");
  755. /*
  756. * Until there's a transition from loop down to loop up, treat
  757. * this as loop down only.
  758. */
  759. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  760. atomic_set(&vha->loop_state, LOOP_DOWN);
  761. if (!atomic_read(&vha->loop_down_timer))
  762. atomic_set(&vha->loop_down_timer,
  763. LOOP_DOWN_TIME);
  764. qla2x00_mark_all_devices_lost(vha, 1);
  765. }
  766. if (vha->vp_idx) {
  767. atomic_set(&vha->vp_state, VP_FAILED);
  768. fc_vport_set_state(vha->fc_vport, FC_VPORT_FAILED);
  769. }
  770. if (!(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)))
  771. set_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
  772. set_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags);
  773. set_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags);
  774. ha->flags.gpsc_supported = 1;
  775. vha->flags.management_server_logged_in = 0;
  776. break;
  777. case MBA_CHG_IN_CONNECTION: /* Change in connection mode */
  778. if (IS_QLA2100(ha))
  779. break;
  780. ql_dbg(ql_dbg_async, vha, 0x500f,
  781. "Configuration change detected: value=%x.\n", mb[1]);
  782. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  783. atomic_set(&vha->loop_state, LOOP_DOWN);
  784. if (!atomic_read(&vha->loop_down_timer))
  785. atomic_set(&vha->loop_down_timer,
  786. LOOP_DOWN_TIME);
  787. qla2x00_mark_all_devices_lost(vha, 1);
  788. }
  789. if (vha->vp_idx) {
  790. atomic_set(&vha->vp_state, VP_FAILED);
  791. fc_vport_set_state(vha->fc_vport, FC_VPORT_FAILED);
  792. }
  793. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  794. set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
  795. break;
  796. case MBA_PORT_UPDATE: /* Port database update */
  797. /*
  798. * Handle only global and vn-port update events
  799. *
  800. * Relevant inputs:
  801. * mb[1] = N_Port handle of changed port
  802. * OR 0xffff for global event
  803. * mb[2] = New login state
  804. * 7 = Port logged out
  805. * mb[3] = LSB is vp_idx, 0xff = all vps
  806. *
  807. * Skip processing if:
  808. * Event is global, vp_idx is NOT all vps,
  809. * vp_idx does not match
  810. * Event is not global, vp_idx does not match
  811. */
  812. if (IS_QLA2XXX_MIDTYPE(ha) &&
  813. ((mb[1] == 0xffff && (mb[3] & 0xff) != 0xff) ||
  814. (mb[1] != 0xffff)) && vha->vp_idx != (mb[3] & 0xff))
  815. break;
  816. if (mb[2] == 0x7) {
  817. ql_dbg(ql_dbg_async, vha, 0x5010,
  818. "Port %s %04x %04x %04x.\n",
  819. mb[1] == 0xffff ? "unavailable" : "logout",
  820. mb[1], mb[2], mb[3]);
  821. if (mb[1] == 0xffff)
  822. goto global_port_update;
  823. /* Port logout */
  824. fcport = qla2x00_find_fcport_by_loopid(vha, mb[1]);
  825. if (!fcport)
  826. break;
  827. if (atomic_read(&fcport->state) != FCS_ONLINE)
  828. break;
  829. ql_dbg(ql_dbg_async, vha, 0x508a,
  830. "Marking port lost loopid=%04x portid=%06x.\n",
  831. fcport->loop_id, fcport->d_id.b24);
  832. qla2x00_mark_device_lost(fcport->vha, fcport, 1, 1);
  833. break;
  834. global_port_update:
  835. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  836. atomic_set(&vha->loop_state, LOOP_DOWN);
  837. atomic_set(&vha->loop_down_timer,
  838. LOOP_DOWN_TIME);
  839. vha->device_flags |= DFLG_NO_CABLE;
  840. qla2x00_mark_all_devices_lost(vha, 1);
  841. }
  842. if (vha->vp_idx) {
  843. atomic_set(&vha->vp_state, VP_FAILED);
  844. fc_vport_set_state(vha->fc_vport,
  845. FC_VPORT_FAILED);
  846. qla2x00_mark_all_devices_lost(vha, 1);
  847. }
  848. vha->flags.management_server_logged_in = 0;
  849. ha->link_data_rate = PORT_SPEED_UNKNOWN;
  850. break;
  851. }
  852. /*
  853. * If PORT UPDATE is global (received LIP_OCCURRED/LIP_RESET
  854. * event etc. earlier indicating loop is down) then process
  855. * it. Otherwise ignore it and Wait for RSCN to come in.
  856. */
  857. atomic_set(&vha->loop_down_timer, 0);
  858. if (atomic_read(&vha->loop_state) != LOOP_DOWN &&
  859. atomic_read(&vha->loop_state) != LOOP_DEAD) {
  860. ql_dbg(ql_dbg_async, vha, 0x5011,
  861. "Asynchronous PORT UPDATE ignored %04x/%04x/%04x.\n",
  862. mb[1], mb[2], mb[3]);
  863. qlt_async_event(mb[0], vha, mb);
  864. break;
  865. }
  866. ql_dbg(ql_dbg_async, vha, 0x5012,
  867. "Port database changed %04x %04x %04x.\n",
  868. mb[1], mb[2], mb[3]);
  869. /*
  870. * Mark all devices as missing so we will login again.
  871. */
  872. atomic_set(&vha->loop_state, LOOP_UP);
  873. qla2x00_mark_all_devices_lost(vha, 1);
  874. if (vha->vp_idx == 0 && !qla_ini_mode_enabled(vha))
  875. set_bit(SCR_PENDING, &vha->dpc_flags);
  876. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  877. set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
  878. set_bit(VP_CONFIG_OK, &vha->vp_flags);
  879. qlt_async_event(mb[0], vha, mb);
  880. break;
  881. case MBA_RSCN_UPDATE: /* State Change Registration */
  882. /* Check if the Vport has issued a SCR */
  883. if (vha->vp_idx && test_bit(VP_SCR_NEEDED, &vha->vp_flags))
  884. break;
  885. /* Only handle SCNs for our Vport index. */
  886. if (ha->flags.npiv_supported && vha->vp_idx != (mb[3] & 0xff))
  887. break;
  888. ql_dbg(ql_dbg_async, vha, 0x5013,
  889. "RSCN database changed -- %04x %04x %04x.\n",
  890. mb[1], mb[2], mb[3]);
  891. rscn_entry = ((mb[1] & 0xff) << 16) | mb[2];
  892. host_pid = (vha->d_id.b.domain << 16) | (vha->d_id.b.area << 8)
  893. | vha->d_id.b.al_pa;
  894. if (rscn_entry == host_pid) {
  895. ql_dbg(ql_dbg_async, vha, 0x5014,
  896. "Ignoring RSCN update to local host "
  897. "port ID (%06x).\n", host_pid);
  898. break;
  899. }
  900. /* Ignore reserved bits from RSCN-payload. */
  901. rscn_entry = ((mb[1] & 0x3ff) << 16) | mb[2];
  902. /* Skip RSCNs for virtual ports on the same physical port */
  903. if (qla2x00_is_a_vp_did(vha, rscn_entry))
  904. break;
  905. /*
  906. * Search for the rport related to this RSCN entry and mark it
  907. * as lost.
  908. */
  909. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  910. if (atomic_read(&fcport->state) != FCS_ONLINE)
  911. continue;
  912. if (fcport->d_id.b24 == rscn_entry) {
  913. qla2x00_mark_device_lost(vha, fcport, 0, 0);
  914. break;
  915. }
  916. }
  917. atomic_set(&vha->loop_down_timer, 0);
  918. vha->flags.management_server_logged_in = 0;
  919. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  920. set_bit(RSCN_UPDATE, &vha->dpc_flags);
  921. qla2x00_post_aen_work(vha, FCH_EVT_RSCN, rscn_entry);
  922. break;
  923. /* case MBA_RIO_RESPONSE: */
  924. case MBA_ZIO_RESPONSE:
  925. ql_dbg(ql_dbg_async, vha, 0x5015,
  926. "[R|Z]IO update completion.\n");
  927. if (IS_FWI2_CAPABLE(ha))
  928. qla24xx_process_response_queue(vha, rsp);
  929. else
  930. qla2x00_process_response_queue(rsp);
  931. break;
  932. case MBA_DISCARD_RND_FRAME:
  933. ql_dbg(ql_dbg_async, vha, 0x5016,
  934. "Discard RND Frame -- %04x %04x %04x.\n",
  935. mb[1], mb[2], mb[3]);
  936. break;
  937. case MBA_TRACE_NOTIFICATION:
  938. ql_dbg(ql_dbg_async, vha, 0x5017,
  939. "Trace Notification -- %04x %04x.\n", mb[1], mb[2]);
  940. break;
  941. case MBA_ISP84XX_ALERT:
  942. ql_dbg(ql_dbg_async, vha, 0x5018,
  943. "ISP84XX Alert Notification -- %04x %04x %04x.\n",
  944. mb[1], mb[2], mb[3]);
  945. spin_lock_irqsave(&ha->cs84xx->access_lock, flags);
  946. switch (mb[1]) {
  947. case A84_PANIC_RECOVERY:
  948. ql_log(ql_log_info, vha, 0x5019,
  949. "Alert 84XX: panic recovery %04x %04x.\n",
  950. mb[2], mb[3]);
  951. break;
  952. case A84_OP_LOGIN_COMPLETE:
  953. ha->cs84xx->op_fw_version = mb[3] << 16 | mb[2];
  954. ql_log(ql_log_info, vha, 0x501a,
  955. "Alert 84XX: firmware version %x.\n",
  956. ha->cs84xx->op_fw_version);
  957. break;
  958. case A84_DIAG_LOGIN_COMPLETE:
  959. ha->cs84xx->diag_fw_version = mb[3] << 16 | mb[2];
  960. ql_log(ql_log_info, vha, 0x501b,
  961. "Alert 84XX: diagnostic firmware version %x.\n",
  962. ha->cs84xx->diag_fw_version);
  963. break;
  964. case A84_GOLD_LOGIN_COMPLETE:
  965. ha->cs84xx->diag_fw_version = mb[3] << 16 | mb[2];
  966. ha->cs84xx->fw_update = 1;
  967. ql_log(ql_log_info, vha, 0x501c,
  968. "Alert 84XX: gold firmware version %x.\n",
  969. ha->cs84xx->gold_fw_version);
  970. break;
  971. default:
  972. ql_log(ql_log_warn, vha, 0x501d,
  973. "Alert 84xx: Invalid Alert %04x %04x %04x.\n",
  974. mb[1], mb[2], mb[3]);
  975. }
  976. spin_unlock_irqrestore(&ha->cs84xx->access_lock, flags);
  977. break;
  978. case MBA_DCBX_START:
  979. ql_dbg(ql_dbg_async, vha, 0x501e,
  980. "DCBX Started -- %04x %04x %04x.\n",
  981. mb[1], mb[2], mb[3]);
  982. break;
  983. case MBA_DCBX_PARAM_UPDATE:
  984. ql_dbg(ql_dbg_async, vha, 0x501f,
  985. "DCBX Parameters Updated -- %04x %04x %04x.\n",
  986. mb[1], mb[2], mb[3]);
  987. break;
  988. case MBA_FCF_CONF_ERR:
  989. ql_dbg(ql_dbg_async, vha, 0x5020,
  990. "FCF Configuration Error -- %04x %04x %04x.\n",
  991. mb[1], mb[2], mb[3]);
  992. break;
  993. case MBA_IDC_NOTIFY:
  994. if (IS_QLA8031(vha->hw) || IS_QLA8044(ha)) {
  995. mb[4] = RD_REG_WORD(&reg24->mailbox4);
  996. if (((mb[2] & 0x7fff) == MBC_PORT_RESET ||
  997. (mb[2] & 0x7fff) == MBC_SET_PORT_CONFIG) &&
  998. (mb[4] & INTERNAL_LOOPBACK_MASK) != 0) {
  999. set_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags);
  1000. /*
  1001. * Extend loop down timer since port is active.
  1002. */
  1003. if (atomic_read(&vha->loop_state) == LOOP_DOWN)
  1004. atomic_set(&vha->loop_down_timer,
  1005. LOOP_DOWN_TIME);
  1006. qla2xxx_wake_dpc(vha);
  1007. }
  1008. }
  1009. case MBA_IDC_COMPLETE:
  1010. if (ha->notify_lb_portup_comp && !vha->vp_idx)
  1011. complete(&ha->lb_portup_comp);
  1012. /* Fallthru */
  1013. case MBA_IDC_TIME_EXT:
  1014. if (IS_QLA81XX(vha->hw) || IS_QLA8031(vha->hw) ||
  1015. IS_QLA8044(ha))
  1016. qla81xx_idc_event(vha, mb[0], mb[1]);
  1017. break;
  1018. case MBA_IDC_AEN:
  1019. mb[4] = RD_REG_WORD(&reg24->mailbox4);
  1020. mb[5] = RD_REG_WORD(&reg24->mailbox5);
  1021. mb[6] = RD_REG_WORD(&reg24->mailbox6);
  1022. mb[7] = RD_REG_WORD(&reg24->mailbox7);
  1023. qla83xx_handle_8200_aen(vha, mb);
  1024. break;
  1025. case MBA_DPORT_DIAGNOSTICS:
  1026. ql_dbg(ql_dbg_async, vha, 0x5052,
  1027. "D-Port Diagnostics: %04x result=%s\n",
  1028. mb[0],
  1029. mb[1] == 0 ? "start" :
  1030. mb[1] == 1 ? "done (pass)" :
  1031. mb[1] == 2 ? "done (error)" : "other");
  1032. break;
  1033. case MBA_TEMPERATURE_ALERT:
  1034. ql_dbg(ql_dbg_async, vha, 0x505e,
  1035. "TEMPERATURE ALERT: %04x %04x %04x\n", mb[1], mb[2], mb[3]);
  1036. if (mb[1] == 0x12)
  1037. schedule_work(&ha->board_disable);
  1038. break;
  1039. default:
  1040. ql_dbg(ql_dbg_async, vha, 0x5057,
  1041. "Unknown AEN:%04x %04x %04x %04x\n",
  1042. mb[0], mb[1], mb[2], mb[3]);
  1043. }
  1044. qlt_async_event(mb[0], vha, mb);
  1045. if (!vha->vp_idx && ha->num_vhosts)
  1046. qla2x00_alert_all_vps(rsp, mb);
  1047. }
  1048. /**
  1049. * qla2x00_process_completed_request() - Process a Fast Post response.
  1050. * @ha: SCSI driver HA context
  1051. * @index: SRB index
  1052. */
  1053. void
  1054. qla2x00_process_completed_request(struct scsi_qla_host *vha,
  1055. struct req_que *req, uint32_t index)
  1056. {
  1057. srb_t *sp;
  1058. struct qla_hw_data *ha = vha->hw;
  1059. /* Validate handle. */
  1060. if (index >= req->num_outstanding_cmds) {
  1061. ql_log(ql_log_warn, vha, 0x3014,
  1062. "Invalid SCSI command index (%x).\n", index);
  1063. if (IS_P3P_TYPE(ha))
  1064. set_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags);
  1065. else
  1066. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1067. return;
  1068. }
  1069. sp = req->outstanding_cmds[index];
  1070. if (sp) {
  1071. /* Free outstanding command slot. */
  1072. req->outstanding_cmds[index] = NULL;
  1073. /* Save ISP completion status */
  1074. sp->done(ha, sp, DID_OK << 16);
  1075. } else {
  1076. ql_log(ql_log_warn, vha, 0x3016, "Invalid SCSI SRB.\n");
  1077. if (IS_P3P_TYPE(ha))
  1078. set_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags);
  1079. else
  1080. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1081. }
  1082. }
  1083. srb_t *
  1084. qla2x00_get_sp_from_handle(scsi_qla_host_t *vha, const char *func,
  1085. struct req_que *req, void *iocb)
  1086. {
  1087. struct qla_hw_data *ha = vha->hw;
  1088. sts_entry_t *pkt = iocb;
  1089. srb_t *sp = NULL;
  1090. uint16_t index;
  1091. index = LSW(pkt->handle);
  1092. if (index >= req->num_outstanding_cmds) {
  1093. ql_log(ql_log_warn, vha, 0x5031,
  1094. "Invalid command index (%x).\n", index);
  1095. if (IS_P3P_TYPE(ha))
  1096. set_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags);
  1097. else
  1098. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1099. goto done;
  1100. }
  1101. sp = req->outstanding_cmds[index];
  1102. if (!sp) {
  1103. ql_log(ql_log_warn, vha, 0x5032,
  1104. "Invalid completion handle (%x) -- timed-out.\n", index);
  1105. return sp;
  1106. }
  1107. if (sp->handle != index) {
  1108. ql_log(ql_log_warn, vha, 0x5033,
  1109. "SRB handle (%x) mismatch %x.\n", sp->handle, index);
  1110. return NULL;
  1111. }
  1112. req->outstanding_cmds[index] = NULL;
  1113. done:
  1114. return sp;
  1115. }
  1116. static void
  1117. qla2x00_mbx_iocb_entry(scsi_qla_host_t *vha, struct req_que *req,
  1118. struct mbx_entry *mbx)
  1119. {
  1120. const char func[] = "MBX-IOCB";
  1121. const char *type;
  1122. fc_port_t *fcport;
  1123. srb_t *sp;
  1124. struct srb_iocb *lio;
  1125. uint16_t *data;
  1126. uint16_t status;
  1127. sp = qla2x00_get_sp_from_handle(vha, func, req, mbx);
  1128. if (!sp)
  1129. return;
  1130. lio = &sp->u.iocb_cmd;
  1131. type = sp->name;
  1132. fcport = sp->fcport;
  1133. data = lio->u.logio.data;
  1134. data[0] = MBS_COMMAND_ERROR;
  1135. data[1] = lio->u.logio.flags & SRB_LOGIN_RETRIED ?
  1136. QLA_LOGIO_LOGIN_RETRIED : 0;
  1137. if (mbx->entry_status) {
  1138. ql_dbg(ql_dbg_async, vha, 0x5043,
  1139. "Async-%s error entry - hdl=%x portid=%02x%02x%02x "
  1140. "entry-status=%x status=%x state-flag=%x "
  1141. "status-flags=%x.\n", type, sp->handle,
  1142. fcport->d_id.b.domain, fcport->d_id.b.area,
  1143. fcport->d_id.b.al_pa, mbx->entry_status,
  1144. le16_to_cpu(mbx->status), le16_to_cpu(mbx->state_flags),
  1145. le16_to_cpu(mbx->status_flags));
  1146. ql_dump_buffer(ql_dbg_async + ql_dbg_buffer, vha, 0x5029,
  1147. (uint8_t *)mbx, sizeof(*mbx));
  1148. goto logio_done;
  1149. }
  1150. status = le16_to_cpu(mbx->status);
  1151. if (status == 0x30 && sp->type == SRB_LOGIN_CMD &&
  1152. le16_to_cpu(mbx->mb0) == MBS_COMMAND_COMPLETE)
  1153. status = 0;
  1154. if (!status && le16_to_cpu(mbx->mb0) == MBS_COMMAND_COMPLETE) {
  1155. ql_dbg(ql_dbg_async, vha, 0x5045,
  1156. "Async-%s complete - hdl=%x portid=%02x%02x%02x mbx1=%x.\n",
  1157. type, sp->handle, fcport->d_id.b.domain,
  1158. fcport->d_id.b.area, fcport->d_id.b.al_pa,
  1159. le16_to_cpu(mbx->mb1));
  1160. data[0] = MBS_COMMAND_COMPLETE;
  1161. if (sp->type == SRB_LOGIN_CMD) {
  1162. fcport->port_type = FCT_TARGET;
  1163. if (le16_to_cpu(mbx->mb1) & BIT_0)
  1164. fcport->port_type = FCT_INITIATOR;
  1165. else if (le16_to_cpu(mbx->mb1) & BIT_1)
  1166. fcport->flags |= FCF_FCP2_DEVICE;
  1167. }
  1168. goto logio_done;
  1169. }
  1170. data[0] = le16_to_cpu(mbx->mb0);
  1171. switch (data[0]) {
  1172. case MBS_PORT_ID_USED:
  1173. data[1] = le16_to_cpu(mbx->mb1);
  1174. break;
  1175. case MBS_LOOP_ID_USED:
  1176. break;
  1177. default:
  1178. data[0] = MBS_COMMAND_ERROR;
  1179. break;
  1180. }
  1181. ql_log(ql_log_warn, vha, 0x5046,
  1182. "Async-%s failed - hdl=%x portid=%02x%02x%02x status=%x "
  1183. "mb0=%x mb1=%x mb2=%x mb6=%x mb7=%x.\n", type, sp->handle,
  1184. fcport->d_id.b.domain, fcport->d_id.b.area, fcport->d_id.b.al_pa,
  1185. status, le16_to_cpu(mbx->mb0), le16_to_cpu(mbx->mb1),
  1186. le16_to_cpu(mbx->mb2), le16_to_cpu(mbx->mb6),
  1187. le16_to_cpu(mbx->mb7));
  1188. logio_done:
  1189. sp->done(vha, sp, 0);
  1190. }
  1191. static void
  1192. qla2x00_ct_entry(scsi_qla_host_t *vha, struct req_que *req,
  1193. sts_entry_t *pkt, int iocb_type)
  1194. {
  1195. const char func[] = "CT_IOCB";
  1196. const char *type;
  1197. srb_t *sp;
  1198. struct fc_bsg_job *bsg_job;
  1199. uint16_t comp_status;
  1200. int res;
  1201. sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
  1202. if (!sp)
  1203. return;
  1204. bsg_job = sp->u.bsg_job;
  1205. type = "ct pass-through";
  1206. comp_status = le16_to_cpu(pkt->comp_status);
  1207. /* return FC_CTELS_STATUS_OK and leave the decoding of the ELS/CT
  1208. * fc payload to the caller
  1209. */
  1210. bsg_job->reply->reply_data.ctels_reply.status = FC_CTELS_STATUS_OK;
  1211. bsg_job->reply_len = sizeof(struct fc_bsg_reply);
  1212. if (comp_status != CS_COMPLETE) {
  1213. if (comp_status == CS_DATA_UNDERRUN) {
  1214. res = DID_OK << 16;
  1215. bsg_job->reply->reply_payload_rcv_len =
  1216. le16_to_cpu(((sts_entry_t *)pkt)->rsp_info_len);
  1217. ql_log(ql_log_warn, vha, 0x5048,
  1218. "CT pass-through-%s error "
  1219. "comp_status-status=0x%x total_byte = 0x%x.\n",
  1220. type, comp_status,
  1221. bsg_job->reply->reply_payload_rcv_len);
  1222. } else {
  1223. ql_log(ql_log_warn, vha, 0x5049,
  1224. "CT pass-through-%s error "
  1225. "comp_status-status=0x%x.\n", type, comp_status);
  1226. res = DID_ERROR << 16;
  1227. bsg_job->reply->reply_payload_rcv_len = 0;
  1228. }
  1229. ql_dump_buffer(ql_dbg_async + ql_dbg_buffer, vha, 0x5035,
  1230. (uint8_t *)pkt, sizeof(*pkt));
  1231. } else {
  1232. res = DID_OK << 16;
  1233. bsg_job->reply->reply_payload_rcv_len =
  1234. bsg_job->reply_payload.payload_len;
  1235. bsg_job->reply_len = 0;
  1236. }
  1237. sp->done(vha, sp, res);
  1238. }
  1239. static void
  1240. qla24xx_els_ct_entry(scsi_qla_host_t *vha, struct req_que *req,
  1241. struct sts_entry_24xx *pkt, int iocb_type)
  1242. {
  1243. const char func[] = "ELS_CT_IOCB";
  1244. const char *type;
  1245. srb_t *sp;
  1246. struct fc_bsg_job *bsg_job;
  1247. uint16_t comp_status;
  1248. uint32_t fw_status[3];
  1249. uint8_t* fw_sts_ptr;
  1250. int res;
  1251. sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
  1252. if (!sp)
  1253. return;
  1254. bsg_job = sp->u.bsg_job;
  1255. type = NULL;
  1256. switch (sp->type) {
  1257. case SRB_ELS_CMD_RPT:
  1258. case SRB_ELS_CMD_HST:
  1259. type = "els";
  1260. break;
  1261. case SRB_CT_CMD:
  1262. type = "ct pass-through";
  1263. break;
  1264. case SRB_ELS_DCMD:
  1265. type = "Driver ELS logo";
  1266. ql_dbg(ql_dbg_user, vha, 0x5047,
  1267. "Completing %s: (%p) type=%d.\n", type, sp, sp->type);
  1268. sp->done(vha, sp, 0);
  1269. return;
  1270. default:
  1271. ql_dbg(ql_dbg_user, vha, 0x503e,
  1272. "Unrecognized SRB: (%p) type=%d.\n", sp, sp->type);
  1273. return;
  1274. }
  1275. comp_status = fw_status[0] = le16_to_cpu(pkt->comp_status);
  1276. fw_status[1] = le16_to_cpu(((struct els_sts_entry_24xx*)pkt)->error_subcode_1);
  1277. fw_status[2] = le16_to_cpu(((struct els_sts_entry_24xx*)pkt)->error_subcode_2);
  1278. /* return FC_CTELS_STATUS_OK and leave the decoding of the ELS/CT
  1279. * fc payload to the caller
  1280. */
  1281. bsg_job->reply->reply_data.ctels_reply.status = FC_CTELS_STATUS_OK;
  1282. bsg_job->reply_len = sizeof(struct fc_bsg_reply) + sizeof(fw_status);
  1283. if (comp_status != CS_COMPLETE) {
  1284. if (comp_status == CS_DATA_UNDERRUN) {
  1285. res = DID_OK << 16;
  1286. bsg_job->reply->reply_payload_rcv_len =
  1287. le16_to_cpu(((struct els_sts_entry_24xx *)pkt)->total_byte_count);
  1288. ql_dbg(ql_dbg_user, vha, 0x503f,
  1289. "ELS-CT pass-through-%s error hdl=%x comp_status-status=0x%x "
  1290. "error subcode 1=0x%x error subcode 2=0x%x total_byte = 0x%x.\n",
  1291. type, sp->handle, comp_status, fw_status[1], fw_status[2],
  1292. le16_to_cpu(((struct els_sts_entry_24xx *)
  1293. pkt)->total_byte_count));
  1294. fw_sts_ptr = ((uint8_t*)bsg_job->req->sense) + sizeof(struct fc_bsg_reply);
  1295. memcpy( fw_sts_ptr, fw_status, sizeof(fw_status));
  1296. }
  1297. else {
  1298. ql_dbg(ql_dbg_user, vha, 0x5040,
  1299. "ELS-CT pass-through-%s error hdl=%x comp_status-status=0x%x "
  1300. "error subcode 1=0x%x error subcode 2=0x%x.\n",
  1301. type, sp->handle, comp_status,
  1302. le16_to_cpu(((struct els_sts_entry_24xx *)
  1303. pkt)->error_subcode_1),
  1304. le16_to_cpu(((struct els_sts_entry_24xx *)
  1305. pkt)->error_subcode_2));
  1306. res = DID_ERROR << 16;
  1307. bsg_job->reply->reply_payload_rcv_len = 0;
  1308. fw_sts_ptr = ((uint8_t*)bsg_job->req->sense) + sizeof(struct fc_bsg_reply);
  1309. memcpy( fw_sts_ptr, fw_status, sizeof(fw_status));
  1310. }
  1311. ql_dump_buffer(ql_dbg_user + ql_dbg_buffer, vha, 0x5056,
  1312. (uint8_t *)pkt, sizeof(*pkt));
  1313. }
  1314. else {
  1315. res = DID_OK << 16;
  1316. bsg_job->reply->reply_payload_rcv_len = bsg_job->reply_payload.payload_len;
  1317. bsg_job->reply_len = 0;
  1318. }
  1319. sp->done(vha, sp, res);
  1320. }
  1321. static void
  1322. qla24xx_logio_entry(scsi_qla_host_t *vha, struct req_que *req,
  1323. struct logio_entry_24xx *logio)
  1324. {
  1325. const char func[] = "LOGIO-IOCB";
  1326. const char *type;
  1327. fc_port_t *fcport;
  1328. srb_t *sp;
  1329. struct srb_iocb *lio;
  1330. uint16_t *data;
  1331. uint32_t iop[2];
  1332. sp = qla2x00_get_sp_from_handle(vha, func, req, logio);
  1333. if (!sp)
  1334. return;
  1335. lio = &sp->u.iocb_cmd;
  1336. type = sp->name;
  1337. fcport = sp->fcport;
  1338. data = lio->u.logio.data;
  1339. data[0] = MBS_COMMAND_ERROR;
  1340. data[1] = lio->u.logio.flags & SRB_LOGIN_RETRIED ?
  1341. QLA_LOGIO_LOGIN_RETRIED : 0;
  1342. if (logio->entry_status) {
  1343. ql_log(ql_log_warn, fcport->vha, 0x5034,
  1344. "Async-%s error entry - hdl=%x"
  1345. "portid=%02x%02x%02x entry-status=%x.\n",
  1346. type, sp->handle, fcport->d_id.b.domain,
  1347. fcport->d_id.b.area, fcport->d_id.b.al_pa,
  1348. logio->entry_status);
  1349. ql_dump_buffer(ql_dbg_async + ql_dbg_buffer, vha, 0x504d,
  1350. (uint8_t *)logio, sizeof(*logio));
  1351. goto logio_done;
  1352. }
  1353. if (le16_to_cpu(logio->comp_status) == CS_COMPLETE) {
  1354. ql_dbg(ql_dbg_async, fcport->vha, 0x5036,
  1355. "Async-%s complete - hdl=%x portid=%02x%02x%02x "
  1356. "iop0=%x.\n", type, sp->handle, fcport->d_id.b.domain,
  1357. fcport->d_id.b.area, fcport->d_id.b.al_pa,
  1358. le32_to_cpu(logio->io_parameter[0]));
  1359. data[0] = MBS_COMMAND_COMPLETE;
  1360. if (sp->type != SRB_LOGIN_CMD)
  1361. goto logio_done;
  1362. iop[0] = le32_to_cpu(logio->io_parameter[0]);
  1363. if (iop[0] & BIT_4) {
  1364. fcport->port_type = FCT_TARGET;
  1365. if (iop[0] & BIT_8)
  1366. fcport->flags |= FCF_FCP2_DEVICE;
  1367. } else if (iop[0] & BIT_5)
  1368. fcport->port_type = FCT_INITIATOR;
  1369. if (iop[0] & BIT_7)
  1370. fcport->flags |= FCF_CONF_COMP_SUPPORTED;
  1371. if (logio->io_parameter[7] || logio->io_parameter[8])
  1372. fcport->supported_classes |= FC_COS_CLASS2;
  1373. if (logio->io_parameter[9] || logio->io_parameter[10])
  1374. fcport->supported_classes |= FC_COS_CLASS3;
  1375. goto logio_done;
  1376. }
  1377. iop[0] = le32_to_cpu(logio->io_parameter[0]);
  1378. iop[1] = le32_to_cpu(logio->io_parameter[1]);
  1379. switch (iop[0]) {
  1380. case LSC_SCODE_PORTID_USED:
  1381. data[0] = MBS_PORT_ID_USED;
  1382. data[1] = LSW(iop[1]);
  1383. break;
  1384. case LSC_SCODE_NPORT_USED:
  1385. data[0] = MBS_LOOP_ID_USED;
  1386. break;
  1387. default:
  1388. data[0] = MBS_COMMAND_ERROR;
  1389. break;
  1390. }
  1391. ql_dbg(ql_dbg_async, fcport->vha, 0x5037,
  1392. "Async-%s failed - hdl=%x portid=%02x%02x%02x comp=%x "
  1393. "iop0=%x iop1=%x.\n", type, sp->handle, fcport->d_id.b.domain,
  1394. fcport->d_id.b.area, fcport->d_id.b.al_pa,
  1395. le16_to_cpu(logio->comp_status),
  1396. le32_to_cpu(logio->io_parameter[0]),
  1397. le32_to_cpu(logio->io_parameter[1]));
  1398. logio_done:
  1399. sp->done(vha, sp, 0);
  1400. }
  1401. static void
  1402. qla24xx_tm_iocb_entry(scsi_qla_host_t *vha, struct req_que *req, void *tsk)
  1403. {
  1404. const char func[] = "TMF-IOCB";
  1405. const char *type;
  1406. fc_port_t *fcport;
  1407. srb_t *sp;
  1408. struct srb_iocb *iocb;
  1409. struct sts_entry_24xx *sts = (struct sts_entry_24xx *)tsk;
  1410. sp = qla2x00_get_sp_from_handle(vha, func, req, tsk);
  1411. if (!sp)
  1412. return;
  1413. iocb = &sp->u.iocb_cmd;
  1414. type = sp->name;
  1415. fcport = sp->fcport;
  1416. iocb->u.tmf.data = QLA_SUCCESS;
  1417. if (sts->entry_status) {
  1418. ql_log(ql_log_warn, fcport->vha, 0x5038,
  1419. "Async-%s error - hdl=%x entry-status(%x).\n",
  1420. type, sp->handle, sts->entry_status);
  1421. iocb->u.tmf.data = QLA_FUNCTION_FAILED;
  1422. } else if (sts->comp_status != cpu_to_le16(CS_COMPLETE)) {
  1423. ql_log(ql_log_warn, fcport->vha, 0x5039,
  1424. "Async-%s error - hdl=%x completion status(%x).\n",
  1425. type, sp->handle, sts->comp_status);
  1426. iocb->u.tmf.data = QLA_FUNCTION_FAILED;
  1427. } else if ((le16_to_cpu(sts->scsi_status) &
  1428. SS_RESPONSE_INFO_LEN_VALID)) {
  1429. if (le32_to_cpu(sts->rsp_data_len) < 4) {
  1430. ql_log(ql_log_warn, fcport->vha, 0x503b,
  1431. "Async-%s error - hdl=%x not enough response(%d).\n",
  1432. type, sp->handle, sts->rsp_data_len);
  1433. } else if (sts->data[3]) {
  1434. ql_log(ql_log_warn, fcport->vha, 0x503c,
  1435. "Async-%s error - hdl=%x response(%x).\n",
  1436. type, sp->handle, sts->data[3]);
  1437. iocb->u.tmf.data = QLA_FUNCTION_FAILED;
  1438. }
  1439. }
  1440. if (iocb->u.tmf.data != QLA_SUCCESS)
  1441. ql_dump_buffer(ql_dbg_async + ql_dbg_buffer, vha, 0x5055,
  1442. (uint8_t *)sts, sizeof(*sts));
  1443. sp->done(vha, sp, 0);
  1444. }
  1445. /**
  1446. * qla2x00_process_response_queue() - Process response queue entries.
  1447. * @ha: SCSI driver HA context
  1448. */
  1449. void
  1450. qla2x00_process_response_queue(struct rsp_que *rsp)
  1451. {
  1452. struct scsi_qla_host *vha;
  1453. struct qla_hw_data *ha = rsp->hw;
  1454. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  1455. sts_entry_t *pkt;
  1456. uint16_t handle_cnt;
  1457. uint16_t cnt;
  1458. vha = pci_get_drvdata(ha->pdev);
  1459. if (!vha->flags.online)
  1460. return;
  1461. while (rsp->ring_ptr->signature != RESPONSE_PROCESSED) {
  1462. pkt = (sts_entry_t *)rsp->ring_ptr;
  1463. rsp->ring_index++;
  1464. if (rsp->ring_index == rsp->length) {
  1465. rsp->ring_index = 0;
  1466. rsp->ring_ptr = rsp->ring;
  1467. } else {
  1468. rsp->ring_ptr++;
  1469. }
  1470. if (pkt->entry_status != 0) {
  1471. qla2x00_error_entry(vha, rsp, pkt);
  1472. ((response_t *)pkt)->signature = RESPONSE_PROCESSED;
  1473. wmb();
  1474. continue;
  1475. }
  1476. switch (pkt->entry_type) {
  1477. case STATUS_TYPE:
  1478. qla2x00_status_entry(vha, rsp, pkt);
  1479. break;
  1480. case STATUS_TYPE_21:
  1481. handle_cnt = ((sts21_entry_t *)pkt)->handle_count;
  1482. for (cnt = 0; cnt < handle_cnt; cnt++) {
  1483. qla2x00_process_completed_request(vha, rsp->req,
  1484. ((sts21_entry_t *)pkt)->handle[cnt]);
  1485. }
  1486. break;
  1487. case STATUS_TYPE_22:
  1488. handle_cnt = ((sts22_entry_t *)pkt)->handle_count;
  1489. for (cnt = 0; cnt < handle_cnt; cnt++) {
  1490. qla2x00_process_completed_request(vha, rsp->req,
  1491. ((sts22_entry_t *)pkt)->handle[cnt]);
  1492. }
  1493. break;
  1494. case STATUS_CONT_TYPE:
  1495. qla2x00_status_cont_entry(rsp, (sts_cont_entry_t *)pkt);
  1496. break;
  1497. case MBX_IOCB_TYPE:
  1498. qla2x00_mbx_iocb_entry(vha, rsp->req,
  1499. (struct mbx_entry *)pkt);
  1500. break;
  1501. case CT_IOCB_TYPE:
  1502. qla2x00_ct_entry(vha, rsp->req, pkt, CT_IOCB_TYPE);
  1503. break;
  1504. default:
  1505. /* Type Not Supported. */
  1506. ql_log(ql_log_warn, vha, 0x504a,
  1507. "Received unknown response pkt type %x "
  1508. "entry status=%x.\n",
  1509. pkt->entry_type, pkt->entry_status);
  1510. break;
  1511. }
  1512. ((response_t *)pkt)->signature = RESPONSE_PROCESSED;
  1513. wmb();
  1514. }
  1515. /* Adjust ring index */
  1516. WRT_REG_WORD(ISP_RSP_Q_OUT(ha, reg), rsp->ring_index);
  1517. }
  1518. static inline void
  1519. qla2x00_handle_sense(srb_t *sp, uint8_t *sense_data, uint32_t par_sense_len,
  1520. uint32_t sense_len, struct rsp_que *rsp, int res)
  1521. {
  1522. struct scsi_qla_host *vha = sp->fcport->vha;
  1523. struct scsi_cmnd *cp = GET_CMD_SP(sp);
  1524. uint32_t track_sense_len;
  1525. if (sense_len >= SCSI_SENSE_BUFFERSIZE)
  1526. sense_len = SCSI_SENSE_BUFFERSIZE;
  1527. SET_CMD_SENSE_LEN(sp, sense_len);
  1528. SET_CMD_SENSE_PTR(sp, cp->sense_buffer);
  1529. track_sense_len = sense_len;
  1530. if (sense_len > par_sense_len)
  1531. sense_len = par_sense_len;
  1532. memcpy(cp->sense_buffer, sense_data, sense_len);
  1533. SET_CMD_SENSE_PTR(sp, cp->sense_buffer + sense_len);
  1534. track_sense_len -= sense_len;
  1535. SET_CMD_SENSE_LEN(sp, track_sense_len);
  1536. if (track_sense_len != 0) {
  1537. rsp->status_srb = sp;
  1538. cp->result = res;
  1539. }
  1540. if (sense_len) {
  1541. ql_dbg(ql_dbg_io + ql_dbg_buffer, vha, 0x301c,
  1542. "Check condition Sense data, nexus%ld:%d:%llu cmd=%p.\n",
  1543. sp->fcport->vha->host_no, cp->device->id, cp->device->lun,
  1544. cp);
  1545. ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x302b,
  1546. cp->sense_buffer, sense_len);
  1547. }
  1548. }
  1549. struct scsi_dif_tuple {
  1550. __be16 guard; /* Checksum */
  1551. __be16 app_tag; /* APPL identifier */
  1552. __be32 ref_tag; /* Target LBA or indirect LBA */
  1553. };
  1554. /*
  1555. * Checks the guard or meta-data for the type of error
  1556. * detected by the HBA. In case of errors, we set the
  1557. * ASC/ASCQ fields in the sense buffer with ILLEGAL_REQUEST
  1558. * to indicate to the kernel that the HBA detected error.
  1559. */
  1560. static inline int
  1561. qla2x00_handle_dif_error(srb_t *sp, struct sts_entry_24xx *sts24)
  1562. {
  1563. struct scsi_qla_host *vha = sp->fcport->vha;
  1564. struct scsi_cmnd *cmd = GET_CMD_SP(sp);
  1565. uint8_t *ap = &sts24->data[12];
  1566. uint8_t *ep = &sts24->data[20];
  1567. uint32_t e_ref_tag, a_ref_tag;
  1568. uint16_t e_app_tag, a_app_tag;
  1569. uint16_t e_guard, a_guard;
  1570. /*
  1571. * swab32 of the "data" field in the beginning of qla2x00_status_entry()
  1572. * would make guard field appear at offset 2
  1573. */
  1574. a_guard = le16_to_cpu(*(uint16_t *)(ap + 2));
  1575. a_app_tag = le16_to_cpu(*(uint16_t *)(ap + 0));
  1576. a_ref_tag = le32_to_cpu(*(uint32_t *)(ap + 4));
  1577. e_guard = le16_to_cpu(*(uint16_t *)(ep + 2));
  1578. e_app_tag = le16_to_cpu(*(uint16_t *)(ep + 0));
  1579. e_ref_tag = le32_to_cpu(*(uint32_t *)(ep + 4));
  1580. ql_dbg(ql_dbg_io, vha, 0x3023,
  1581. "iocb(s) %p Returned STATUS.\n", sts24);
  1582. ql_dbg(ql_dbg_io, vha, 0x3024,
  1583. "DIF ERROR in cmd 0x%x lba 0x%llx act ref"
  1584. " tag=0x%x, exp ref_tag=0x%x, act app tag=0x%x, exp app"
  1585. " tag=0x%x, act guard=0x%x, exp guard=0x%x.\n",
  1586. cmd->cmnd[0], (u64)scsi_get_lba(cmd), a_ref_tag, e_ref_tag,
  1587. a_app_tag, e_app_tag, a_guard, e_guard);
  1588. /*
  1589. * Ignore sector if:
  1590. * For type 3: ref & app tag is all 'f's
  1591. * For type 0,1,2: app tag is all 'f's
  1592. */
  1593. if ((a_app_tag == 0xffff) &&
  1594. ((scsi_get_prot_type(cmd) != SCSI_PROT_DIF_TYPE3) ||
  1595. (a_ref_tag == 0xffffffff))) {
  1596. uint32_t blocks_done, resid;
  1597. sector_t lba_s = scsi_get_lba(cmd);
  1598. /* 2TB boundary case covered automatically with this */
  1599. blocks_done = e_ref_tag - (uint32_t)lba_s + 1;
  1600. resid = scsi_bufflen(cmd) - (blocks_done *
  1601. cmd->device->sector_size);
  1602. scsi_set_resid(cmd, resid);
  1603. cmd->result = DID_OK << 16;
  1604. /* Update protection tag */
  1605. if (scsi_prot_sg_count(cmd)) {
  1606. uint32_t i, j = 0, k = 0, num_ent;
  1607. struct scatterlist *sg;
  1608. struct t10_pi_tuple *spt;
  1609. /* Patch the corresponding protection tags */
  1610. scsi_for_each_prot_sg(cmd, sg,
  1611. scsi_prot_sg_count(cmd), i) {
  1612. num_ent = sg_dma_len(sg) / 8;
  1613. if (k + num_ent < blocks_done) {
  1614. k += num_ent;
  1615. continue;
  1616. }
  1617. j = blocks_done - k - 1;
  1618. k = blocks_done;
  1619. break;
  1620. }
  1621. if (k != blocks_done) {
  1622. ql_log(ql_log_warn, vha, 0x302f,
  1623. "unexpected tag values tag:lba=%x:%llx)\n",
  1624. e_ref_tag, (unsigned long long)lba_s);
  1625. return 1;
  1626. }
  1627. spt = page_address(sg_page(sg)) + sg->offset;
  1628. spt += j;
  1629. spt->app_tag = 0xffff;
  1630. if (scsi_get_prot_type(cmd) == SCSI_PROT_DIF_TYPE3)
  1631. spt->ref_tag = 0xffffffff;
  1632. }
  1633. return 0;
  1634. }
  1635. /* check guard */
  1636. if (e_guard != a_guard) {
  1637. scsi_build_sense_buffer(1, cmd->sense_buffer, ILLEGAL_REQUEST,
  1638. 0x10, 0x1);
  1639. set_driver_byte(cmd, DRIVER_SENSE);
  1640. set_host_byte(cmd, DID_ABORT);
  1641. cmd->result |= SAM_STAT_CHECK_CONDITION << 1;
  1642. return 1;
  1643. }
  1644. /* check ref tag */
  1645. if (e_ref_tag != a_ref_tag) {
  1646. scsi_build_sense_buffer(1, cmd->sense_buffer, ILLEGAL_REQUEST,
  1647. 0x10, 0x3);
  1648. set_driver_byte(cmd, DRIVER_SENSE);
  1649. set_host_byte(cmd, DID_ABORT);
  1650. cmd->result |= SAM_STAT_CHECK_CONDITION << 1;
  1651. return 1;
  1652. }
  1653. /* check appl tag */
  1654. if (e_app_tag != a_app_tag) {
  1655. scsi_build_sense_buffer(1, cmd->sense_buffer, ILLEGAL_REQUEST,
  1656. 0x10, 0x2);
  1657. set_driver_byte(cmd, DRIVER_SENSE);
  1658. set_host_byte(cmd, DID_ABORT);
  1659. cmd->result |= SAM_STAT_CHECK_CONDITION << 1;
  1660. return 1;
  1661. }
  1662. return 1;
  1663. }
  1664. static void
  1665. qla25xx_process_bidir_status_iocb(scsi_qla_host_t *vha, void *pkt,
  1666. struct req_que *req, uint32_t index)
  1667. {
  1668. struct qla_hw_data *ha = vha->hw;
  1669. srb_t *sp;
  1670. uint16_t comp_status;
  1671. uint16_t scsi_status;
  1672. uint16_t thread_id;
  1673. uint32_t rval = EXT_STATUS_OK;
  1674. struct fc_bsg_job *bsg_job = NULL;
  1675. sts_entry_t *sts;
  1676. struct sts_entry_24xx *sts24;
  1677. sts = (sts_entry_t *) pkt;
  1678. sts24 = (struct sts_entry_24xx *) pkt;
  1679. /* Validate handle. */
  1680. if (index >= req->num_outstanding_cmds) {
  1681. ql_log(ql_log_warn, vha, 0x70af,
  1682. "Invalid SCSI completion handle 0x%x.\n", index);
  1683. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1684. return;
  1685. }
  1686. sp = req->outstanding_cmds[index];
  1687. if (sp) {
  1688. /* Free outstanding command slot. */
  1689. req->outstanding_cmds[index] = NULL;
  1690. bsg_job = sp->u.bsg_job;
  1691. } else {
  1692. ql_log(ql_log_warn, vha, 0x70b0,
  1693. "Req:%d: Invalid ISP SCSI completion handle(0x%x)\n",
  1694. req->id, index);
  1695. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1696. return;
  1697. }
  1698. if (IS_FWI2_CAPABLE(ha)) {
  1699. comp_status = le16_to_cpu(sts24->comp_status);
  1700. scsi_status = le16_to_cpu(sts24->scsi_status) & SS_MASK;
  1701. } else {
  1702. comp_status = le16_to_cpu(sts->comp_status);
  1703. scsi_status = le16_to_cpu(sts->scsi_status) & SS_MASK;
  1704. }
  1705. thread_id = bsg_job->request->rqst_data.h_vendor.vendor_cmd[1];
  1706. switch (comp_status) {
  1707. case CS_COMPLETE:
  1708. if (scsi_status == 0) {
  1709. bsg_job->reply->reply_payload_rcv_len =
  1710. bsg_job->reply_payload.payload_len;
  1711. vha->qla_stats.input_bytes +=
  1712. bsg_job->reply->reply_payload_rcv_len;
  1713. vha->qla_stats.input_requests++;
  1714. rval = EXT_STATUS_OK;
  1715. }
  1716. goto done;
  1717. case CS_DATA_OVERRUN:
  1718. ql_dbg(ql_dbg_user, vha, 0x70b1,
  1719. "Command completed with date overrun thread_id=%d\n",
  1720. thread_id);
  1721. rval = EXT_STATUS_DATA_OVERRUN;
  1722. break;
  1723. case CS_DATA_UNDERRUN:
  1724. ql_dbg(ql_dbg_user, vha, 0x70b2,
  1725. "Command completed with date underrun thread_id=%d\n",
  1726. thread_id);
  1727. rval = EXT_STATUS_DATA_UNDERRUN;
  1728. break;
  1729. case CS_BIDIR_RD_OVERRUN:
  1730. ql_dbg(ql_dbg_user, vha, 0x70b3,
  1731. "Command completed with read data overrun thread_id=%d\n",
  1732. thread_id);
  1733. rval = EXT_STATUS_DATA_OVERRUN;
  1734. break;
  1735. case CS_BIDIR_RD_WR_OVERRUN:
  1736. ql_dbg(ql_dbg_user, vha, 0x70b4,
  1737. "Command completed with read and write data overrun "
  1738. "thread_id=%d\n", thread_id);
  1739. rval = EXT_STATUS_DATA_OVERRUN;
  1740. break;
  1741. case CS_BIDIR_RD_OVERRUN_WR_UNDERRUN:
  1742. ql_dbg(ql_dbg_user, vha, 0x70b5,
  1743. "Command completed with read data over and write data "
  1744. "underrun thread_id=%d\n", thread_id);
  1745. rval = EXT_STATUS_DATA_OVERRUN;
  1746. break;
  1747. case CS_BIDIR_RD_UNDERRUN:
  1748. ql_dbg(ql_dbg_user, vha, 0x70b6,
  1749. "Command completed with read data data underrun "
  1750. "thread_id=%d\n", thread_id);
  1751. rval = EXT_STATUS_DATA_UNDERRUN;
  1752. break;
  1753. case CS_BIDIR_RD_UNDERRUN_WR_OVERRUN:
  1754. ql_dbg(ql_dbg_user, vha, 0x70b7,
  1755. "Command completed with read data under and write data "
  1756. "overrun thread_id=%d\n", thread_id);
  1757. rval = EXT_STATUS_DATA_UNDERRUN;
  1758. break;
  1759. case CS_BIDIR_RD_WR_UNDERRUN:
  1760. ql_dbg(ql_dbg_user, vha, 0x70b8,
  1761. "Command completed with read and write data underrun "
  1762. "thread_id=%d\n", thread_id);
  1763. rval = EXT_STATUS_DATA_UNDERRUN;
  1764. break;
  1765. case CS_BIDIR_DMA:
  1766. ql_dbg(ql_dbg_user, vha, 0x70b9,
  1767. "Command completed with data DMA error thread_id=%d\n",
  1768. thread_id);
  1769. rval = EXT_STATUS_DMA_ERR;
  1770. break;
  1771. case CS_TIMEOUT:
  1772. ql_dbg(ql_dbg_user, vha, 0x70ba,
  1773. "Command completed with timeout thread_id=%d\n",
  1774. thread_id);
  1775. rval = EXT_STATUS_TIMEOUT;
  1776. break;
  1777. default:
  1778. ql_dbg(ql_dbg_user, vha, 0x70bb,
  1779. "Command completed with completion status=0x%x "
  1780. "thread_id=%d\n", comp_status, thread_id);
  1781. rval = EXT_STATUS_ERR;
  1782. break;
  1783. }
  1784. bsg_job->reply->reply_payload_rcv_len = 0;
  1785. done:
  1786. /* Return the vendor specific reply to API */
  1787. bsg_job->reply->reply_data.vendor_reply.vendor_rsp[0] = rval;
  1788. bsg_job->reply_len = sizeof(struct fc_bsg_reply);
  1789. /* Always return DID_OK, bsg will send the vendor specific response
  1790. * in this case only */
  1791. sp->done(vha, sp, (DID_OK << 6));
  1792. }
  1793. /**
  1794. * qla2x00_status_entry() - Process a Status IOCB entry.
  1795. * @ha: SCSI driver HA context
  1796. * @pkt: Entry pointer
  1797. */
  1798. static void
  1799. qla2x00_status_entry(scsi_qla_host_t *vha, struct rsp_que *rsp, void *pkt)
  1800. {
  1801. srb_t *sp;
  1802. fc_port_t *fcport;
  1803. struct scsi_cmnd *cp;
  1804. sts_entry_t *sts;
  1805. struct sts_entry_24xx *sts24;
  1806. uint16_t comp_status;
  1807. uint16_t scsi_status;
  1808. uint16_t ox_id;
  1809. uint8_t lscsi_status;
  1810. int32_t resid;
  1811. uint32_t sense_len, par_sense_len, rsp_info_len, resid_len,
  1812. fw_resid_len;
  1813. uint8_t *rsp_info, *sense_data;
  1814. struct qla_hw_data *ha = vha->hw;
  1815. uint32_t handle;
  1816. uint16_t que;
  1817. struct req_que *req;
  1818. int logit = 1;
  1819. int res = 0;
  1820. uint16_t state_flags = 0;
  1821. uint16_t retry_delay = 0;
  1822. sts = (sts_entry_t *) pkt;
  1823. sts24 = (struct sts_entry_24xx *) pkt;
  1824. if (IS_FWI2_CAPABLE(ha)) {
  1825. comp_status = le16_to_cpu(sts24->comp_status);
  1826. scsi_status = le16_to_cpu(sts24->scsi_status) & SS_MASK;
  1827. state_flags = le16_to_cpu(sts24->state_flags);
  1828. } else {
  1829. comp_status = le16_to_cpu(sts->comp_status);
  1830. scsi_status = le16_to_cpu(sts->scsi_status) & SS_MASK;
  1831. }
  1832. handle = (uint32_t) LSW(sts->handle);
  1833. que = MSW(sts->handle);
  1834. req = ha->req_q_map[que];
  1835. /* Check for invalid queue pointer */
  1836. if (req == NULL ||
  1837. que >= find_first_zero_bit(ha->req_qid_map, ha->max_req_queues)) {
  1838. ql_dbg(ql_dbg_io, vha, 0x3059,
  1839. "Invalid status handle (0x%x): Bad req pointer. req=%p, "
  1840. "que=%u.\n", sts->handle, req, que);
  1841. return;
  1842. }
  1843. /* Validate handle. */
  1844. if (handle < req->num_outstanding_cmds) {
  1845. sp = req->outstanding_cmds[handle];
  1846. if (!sp) {
  1847. ql_dbg(ql_dbg_io, vha, 0x3075,
  1848. "%s(%ld): Already returned command for status handle (0x%x).\n",
  1849. __func__, vha->host_no, sts->handle);
  1850. return;
  1851. }
  1852. } else {
  1853. ql_dbg(ql_dbg_io, vha, 0x3017,
  1854. "Invalid status handle, out of range (0x%x).\n",
  1855. sts->handle);
  1856. if (!test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) {
  1857. if (IS_P3P_TYPE(ha))
  1858. set_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags);
  1859. else
  1860. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1861. qla2xxx_wake_dpc(vha);
  1862. }
  1863. return;
  1864. }
  1865. if (unlikely((state_flags & BIT_1) && (sp->type == SRB_BIDI_CMD))) {
  1866. qla25xx_process_bidir_status_iocb(vha, pkt, req, handle);
  1867. return;
  1868. }
  1869. /* Task Management completion. */
  1870. if (sp->type == SRB_TM_CMD) {
  1871. qla24xx_tm_iocb_entry(vha, req, pkt);
  1872. return;
  1873. }
  1874. /* Fast path completion. */
  1875. if (comp_status == CS_COMPLETE && scsi_status == 0) {
  1876. qla2x00_process_completed_request(vha, req, handle);
  1877. return;
  1878. }
  1879. req->outstanding_cmds[handle] = NULL;
  1880. cp = GET_CMD_SP(sp);
  1881. if (cp == NULL) {
  1882. ql_dbg(ql_dbg_io, vha, 0x3018,
  1883. "Command already returned (0x%x/%p).\n",
  1884. sts->handle, sp);
  1885. return;
  1886. }
  1887. lscsi_status = scsi_status & STATUS_MASK;
  1888. fcport = sp->fcport;
  1889. ox_id = 0;
  1890. sense_len = par_sense_len = rsp_info_len = resid_len =
  1891. fw_resid_len = 0;
  1892. if (IS_FWI2_CAPABLE(ha)) {
  1893. if (scsi_status & SS_SENSE_LEN_VALID)
  1894. sense_len = le32_to_cpu(sts24->sense_len);
  1895. if (scsi_status & SS_RESPONSE_INFO_LEN_VALID)
  1896. rsp_info_len = le32_to_cpu(sts24->rsp_data_len);
  1897. if (scsi_status & (SS_RESIDUAL_UNDER | SS_RESIDUAL_OVER))
  1898. resid_len = le32_to_cpu(sts24->rsp_residual_count);
  1899. if (comp_status == CS_DATA_UNDERRUN)
  1900. fw_resid_len = le32_to_cpu(sts24->residual_len);
  1901. rsp_info = sts24->data;
  1902. sense_data = sts24->data;
  1903. host_to_fcp_swap(sts24->data, sizeof(sts24->data));
  1904. ox_id = le16_to_cpu(sts24->ox_id);
  1905. par_sense_len = sizeof(sts24->data);
  1906. /* Valid values of the retry delay timer are 0x1-0xffef */
  1907. if (sts24->retry_delay > 0 && sts24->retry_delay < 0xfff1)
  1908. retry_delay = sts24->retry_delay;
  1909. } else {
  1910. if (scsi_status & SS_SENSE_LEN_VALID)
  1911. sense_len = le16_to_cpu(sts->req_sense_length);
  1912. if (scsi_status & SS_RESPONSE_INFO_LEN_VALID)
  1913. rsp_info_len = le16_to_cpu(sts->rsp_info_len);
  1914. resid_len = le32_to_cpu(sts->residual_length);
  1915. rsp_info = sts->rsp_info;
  1916. sense_data = sts->req_sense_data;
  1917. par_sense_len = sizeof(sts->req_sense_data);
  1918. }
  1919. /* Check for any FCP transport errors. */
  1920. if (scsi_status & SS_RESPONSE_INFO_LEN_VALID) {
  1921. /* Sense data lies beyond any FCP RESPONSE data. */
  1922. if (IS_FWI2_CAPABLE(ha)) {
  1923. sense_data += rsp_info_len;
  1924. par_sense_len -= rsp_info_len;
  1925. }
  1926. if (rsp_info_len > 3 && rsp_info[3]) {
  1927. ql_dbg(ql_dbg_io, fcport->vha, 0x3019,
  1928. "FCP I/O protocol failure (0x%x/0x%x).\n",
  1929. rsp_info_len, rsp_info[3]);
  1930. res = DID_BUS_BUSY << 16;
  1931. goto out;
  1932. }
  1933. }
  1934. /* Check for overrun. */
  1935. if (IS_FWI2_CAPABLE(ha) && comp_status == CS_COMPLETE &&
  1936. scsi_status & SS_RESIDUAL_OVER)
  1937. comp_status = CS_DATA_OVERRUN;
  1938. /*
  1939. * Check retry_delay_timer value if we receive a busy or
  1940. * queue full.
  1941. */
  1942. if (lscsi_status == SAM_STAT_TASK_SET_FULL ||
  1943. lscsi_status == SAM_STAT_BUSY)
  1944. qla2x00_set_retry_delay_timestamp(fcport, retry_delay);
  1945. /*
  1946. * Based on Host and scsi status generate status code for Linux
  1947. */
  1948. switch (comp_status) {
  1949. case CS_COMPLETE:
  1950. case CS_QUEUE_FULL:
  1951. if (scsi_status == 0) {
  1952. res = DID_OK << 16;
  1953. break;
  1954. }
  1955. if (scsi_status & (SS_RESIDUAL_UNDER | SS_RESIDUAL_OVER)) {
  1956. resid = resid_len;
  1957. scsi_set_resid(cp, resid);
  1958. if (!lscsi_status &&
  1959. ((unsigned)(scsi_bufflen(cp) - resid) <
  1960. cp->underflow)) {
  1961. ql_dbg(ql_dbg_io, fcport->vha, 0x301a,
  1962. "Mid-layer underflow "
  1963. "detected (0x%x of 0x%x bytes).\n",
  1964. resid, scsi_bufflen(cp));
  1965. res = DID_ERROR << 16;
  1966. break;
  1967. }
  1968. }
  1969. res = DID_OK << 16 | lscsi_status;
  1970. if (lscsi_status == SAM_STAT_TASK_SET_FULL) {
  1971. ql_dbg(ql_dbg_io, fcport->vha, 0x301b,
  1972. "QUEUE FULL detected.\n");
  1973. break;
  1974. }
  1975. logit = 0;
  1976. if (lscsi_status != SS_CHECK_CONDITION)
  1977. break;
  1978. memset(cp->sense_buffer, 0, SCSI_SENSE_BUFFERSIZE);
  1979. if (!(scsi_status & SS_SENSE_LEN_VALID))
  1980. break;
  1981. qla2x00_handle_sense(sp, sense_data, par_sense_len, sense_len,
  1982. rsp, res);
  1983. break;
  1984. case CS_DATA_UNDERRUN:
  1985. /* Use F/W calculated residual length. */
  1986. resid = IS_FWI2_CAPABLE(ha) ? fw_resid_len : resid_len;
  1987. scsi_set_resid(cp, resid);
  1988. if (scsi_status & SS_RESIDUAL_UNDER) {
  1989. if (IS_FWI2_CAPABLE(ha) && fw_resid_len != resid_len) {
  1990. ql_dbg(ql_dbg_io, fcport->vha, 0x301d,
  1991. "Dropped frame(s) detected "
  1992. "(0x%x of 0x%x bytes).\n",
  1993. resid, scsi_bufflen(cp));
  1994. res = DID_ERROR << 16 | lscsi_status;
  1995. goto check_scsi_status;
  1996. }
  1997. if (!lscsi_status &&
  1998. ((unsigned)(scsi_bufflen(cp) - resid) <
  1999. cp->underflow)) {
  2000. ql_dbg(ql_dbg_io, fcport->vha, 0x301e,
  2001. "Mid-layer underflow "
  2002. "detected (0x%x of 0x%x bytes).\n",
  2003. resid, scsi_bufflen(cp));
  2004. res = DID_ERROR << 16;
  2005. break;
  2006. }
  2007. } else if (lscsi_status != SAM_STAT_TASK_SET_FULL &&
  2008. lscsi_status != SAM_STAT_BUSY) {
  2009. /*
  2010. * scsi status of task set and busy are considered to be
  2011. * task not completed.
  2012. */
  2013. ql_dbg(ql_dbg_io, fcport->vha, 0x301f,
  2014. "Dropped frame(s) detected (0x%x "
  2015. "of 0x%x bytes).\n", resid,
  2016. scsi_bufflen(cp));
  2017. res = DID_ERROR << 16 | lscsi_status;
  2018. goto check_scsi_status;
  2019. } else {
  2020. ql_dbg(ql_dbg_io, fcport->vha, 0x3030,
  2021. "scsi_status: 0x%x, lscsi_status: 0x%x\n",
  2022. scsi_status, lscsi_status);
  2023. }
  2024. res = DID_OK << 16 | lscsi_status;
  2025. logit = 0;
  2026. check_scsi_status:
  2027. /*
  2028. * Check to see if SCSI Status is non zero. If so report SCSI
  2029. * Status.
  2030. */
  2031. if (lscsi_status != 0) {
  2032. if (lscsi_status == SAM_STAT_TASK_SET_FULL) {
  2033. ql_dbg(ql_dbg_io, fcport->vha, 0x3020,
  2034. "QUEUE FULL detected.\n");
  2035. logit = 1;
  2036. break;
  2037. }
  2038. if (lscsi_status != SS_CHECK_CONDITION)
  2039. break;
  2040. memset(cp->sense_buffer, 0, SCSI_SENSE_BUFFERSIZE);
  2041. if (!(scsi_status & SS_SENSE_LEN_VALID))
  2042. break;
  2043. qla2x00_handle_sense(sp, sense_data, par_sense_len,
  2044. sense_len, rsp, res);
  2045. }
  2046. break;
  2047. case CS_PORT_LOGGED_OUT:
  2048. case CS_PORT_CONFIG_CHG:
  2049. case CS_PORT_BUSY:
  2050. case CS_INCOMPLETE:
  2051. case CS_PORT_UNAVAILABLE:
  2052. case CS_TIMEOUT:
  2053. case CS_RESET:
  2054. /*
  2055. * We are going to have the fc class block the rport
  2056. * while we try to recover so instruct the mid layer
  2057. * to requeue until the class decides how to handle this.
  2058. */
  2059. res = DID_TRANSPORT_DISRUPTED << 16;
  2060. if (comp_status == CS_TIMEOUT) {
  2061. if (IS_FWI2_CAPABLE(ha))
  2062. break;
  2063. else if ((le16_to_cpu(sts->status_flags) &
  2064. SF_LOGOUT_SENT) == 0)
  2065. break;
  2066. }
  2067. ql_dbg(ql_dbg_io, fcport->vha, 0x3021,
  2068. "Port to be marked lost on fcport=%02x%02x%02x, current "
  2069. "port state= %s.\n", fcport->d_id.b.domain,
  2070. fcport->d_id.b.area, fcport->d_id.b.al_pa,
  2071. port_state_str[atomic_read(&fcport->state)]);
  2072. if (atomic_read(&fcport->state) == FCS_ONLINE)
  2073. qla2x00_mark_device_lost(fcport->vha, fcport, 1, 1);
  2074. break;
  2075. case CS_ABORTED:
  2076. res = DID_RESET << 16;
  2077. break;
  2078. case CS_DIF_ERROR:
  2079. logit = qla2x00_handle_dif_error(sp, sts24);
  2080. res = cp->result;
  2081. break;
  2082. case CS_TRANSPORT:
  2083. res = DID_ERROR << 16;
  2084. if (!IS_PI_SPLIT_DET_CAPABLE(ha))
  2085. break;
  2086. if (state_flags & BIT_4)
  2087. scmd_printk(KERN_WARNING, cp,
  2088. "Unsupported device '%s' found.\n",
  2089. cp->device->vendor);
  2090. break;
  2091. default:
  2092. res = DID_ERROR << 16;
  2093. break;
  2094. }
  2095. out:
  2096. if (logit)
  2097. ql_dbg(ql_dbg_io, fcport->vha, 0x3022,
  2098. "FCP command status: 0x%x-0x%x (0x%x) nexus=%ld:%d:%llu "
  2099. "portid=%02x%02x%02x oxid=0x%x cdb=%10phN len=0x%x "
  2100. "rsp_info=0x%x resid=0x%x fw_resid=0x%x sp=%p cp=%p.\n",
  2101. comp_status, scsi_status, res, vha->host_no,
  2102. cp->device->id, cp->device->lun, fcport->d_id.b.domain,
  2103. fcport->d_id.b.area, fcport->d_id.b.al_pa, ox_id,
  2104. cp->cmnd, scsi_bufflen(cp), rsp_info_len,
  2105. resid_len, fw_resid_len, sp, cp);
  2106. if (rsp->status_srb == NULL)
  2107. sp->done(ha, sp, res);
  2108. }
  2109. /**
  2110. * qla2x00_status_cont_entry() - Process a Status Continuations entry.
  2111. * @ha: SCSI driver HA context
  2112. * @pkt: Entry pointer
  2113. *
  2114. * Extended sense data.
  2115. */
  2116. static void
  2117. qla2x00_status_cont_entry(struct rsp_que *rsp, sts_cont_entry_t *pkt)
  2118. {
  2119. uint8_t sense_sz = 0;
  2120. struct qla_hw_data *ha = rsp->hw;
  2121. struct scsi_qla_host *vha = pci_get_drvdata(ha->pdev);
  2122. srb_t *sp = rsp->status_srb;
  2123. struct scsi_cmnd *cp;
  2124. uint32_t sense_len;
  2125. uint8_t *sense_ptr;
  2126. if (!sp || !GET_CMD_SENSE_LEN(sp))
  2127. return;
  2128. sense_len = GET_CMD_SENSE_LEN(sp);
  2129. sense_ptr = GET_CMD_SENSE_PTR(sp);
  2130. cp = GET_CMD_SP(sp);
  2131. if (cp == NULL) {
  2132. ql_log(ql_log_warn, vha, 0x3025,
  2133. "cmd is NULL: already returned to OS (sp=%p).\n", sp);
  2134. rsp->status_srb = NULL;
  2135. return;
  2136. }
  2137. if (sense_len > sizeof(pkt->data))
  2138. sense_sz = sizeof(pkt->data);
  2139. else
  2140. sense_sz = sense_len;
  2141. /* Move sense data. */
  2142. if (IS_FWI2_CAPABLE(ha))
  2143. host_to_fcp_swap(pkt->data, sizeof(pkt->data));
  2144. memcpy(sense_ptr, pkt->data, sense_sz);
  2145. ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x302c,
  2146. sense_ptr, sense_sz);
  2147. sense_len -= sense_sz;
  2148. sense_ptr += sense_sz;
  2149. SET_CMD_SENSE_PTR(sp, sense_ptr);
  2150. SET_CMD_SENSE_LEN(sp, sense_len);
  2151. /* Place command on done queue. */
  2152. if (sense_len == 0) {
  2153. rsp->status_srb = NULL;
  2154. sp->done(ha, sp, cp->result);
  2155. }
  2156. }
  2157. /**
  2158. * qla2x00_error_entry() - Process an error entry.
  2159. * @ha: SCSI driver HA context
  2160. * @pkt: Entry pointer
  2161. */
  2162. static void
  2163. qla2x00_error_entry(scsi_qla_host_t *vha, struct rsp_que *rsp, sts_entry_t *pkt)
  2164. {
  2165. srb_t *sp;
  2166. struct qla_hw_data *ha = vha->hw;
  2167. const char func[] = "ERROR-IOCB";
  2168. uint16_t que = MSW(pkt->handle);
  2169. struct req_que *req = NULL;
  2170. int res = DID_ERROR << 16;
  2171. ql_dbg(ql_dbg_async, vha, 0x502a,
  2172. "type of error status in response: 0x%x\n", pkt->entry_status);
  2173. if (que >= ha->max_req_queues || !ha->req_q_map[que])
  2174. goto fatal;
  2175. req = ha->req_q_map[que];
  2176. if (pkt->entry_status & RF_BUSY)
  2177. res = DID_BUS_BUSY << 16;
  2178. if (pkt->entry_type == NOTIFY_ACK_TYPE &&
  2179. pkt->handle == QLA_TGT_SKIP_HANDLE)
  2180. return;
  2181. sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
  2182. if (sp) {
  2183. sp->done(ha, sp, res);
  2184. return;
  2185. }
  2186. fatal:
  2187. ql_log(ql_log_warn, vha, 0x5030,
  2188. "Error entry - invalid handle/queue (%04x).\n", que);
  2189. }
  2190. /**
  2191. * qla24xx_mbx_completion() - Process mailbox command completions.
  2192. * @ha: SCSI driver HA context
  2193. * @mb0: Mailbox0 register
  2194. */
  2195. static void
  2196. qla24xx_mbx_completion(scsi_qla_host_t *vha, uint16_t mb0)
  2197. {
  2198. uint16_t cnt;
  2199. uint32_t mboxes;
  2200. uint16_t __iomem *wptr;
  2201. struct qla_hw_data *ha = vha->hw;
  2202. struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
  2203. /* Read all mbox registers? */
  2204. mboxes = (1 << ha->mbx_count) - 1;
  2205. if (!ha->mcp)
  2206. ql_dbg(ql_dbg_async, vha, 0x504e, "MBX pointer ERROR.\n");
  2207. else
  2208. mboxes = ha->mcp->in_mb;
  2209. /* Load return mailbox registers. */
  2210. ha->flags.mbox_int = 1;
  2211. ha->mailbox_out[0] = mb0;
  2212. mboxes >>= 1;
  2213. wptr = (uint16_t __iomem *)&reg->mailbox1;
  2214. for (cnt = 1; cnt < ha->mbx_count; cnt++) {
  2215. if (mboxes & BIT_0)
  2216. ha->mailbox_out[cnt] = RD_REG_WORD(wptr);
  2217. mboxes >>= 1;
  2218. wptr++;
  2219. }
  2220. }
  2221. static void
  2222. qla24xx_abort_iocb_entry(scsi_qla_host_t *vha, struct req_que *req,
  2223. struct abort_entry_24xx *pkt)
  2224. {
  2225. const char func[] = "ABT_IOCB";
  2226. srb_t *sp;
  2227. struct srb_iocb *abt;
  2228. sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
  2229. if (!sp)
  2230. return;
  2231. abt = &sp->u.iocb_cmd;
  2232. abt->u.abt.comp_status = le32_to_cpu(pkt->nport_handle);
  2233. sp->done(vha, sp, 0);
  2234. }
  2235. /**
  2236. * qla24xx_process_response_queue() - Process response queue entries.
  2237. * @ha: SCSI driver HA context
  2238. */
  2239. void qla24xx_process_response_queue(struct scsi_qla_host *vha,
  2240. struct rsp_que *rsp)
  2241. {
  2242. struct sts_entry_24xx *pkt;
  2243. struct qla_hw_data *ha = vha->hw;
  2244. if (!vha->flags.online)
  2245. return;
  2246. if (rsp->msix && rsp->msix->cpuid != smp_processor_id()) {
  2247. /* if kernel does not notify qla of IRQ's CPU change,
  2248. * then set it here.
  2249. */
  2250. rsp->msix->cpuid = smp_processor_id();
  2251. ha->tgt.rspq_vector_cpuid = rsp->msix->cpuid;
  2252. }
  2253. while (rsp->ring_ptr->signature != RESPONSE_PROCESSED) {
  2254. pkt = (struct sts_entry_24xx *)rsp->ring_ptr;
  2255. rsp->ring_index++;
  2256. if (rsp->ring_index == rsp->length) {
  2257. rsp->ring_index = 0;
  2258. rsp->ring_ptr = rsp->ring;
  2259. } else {
  2260. rsp->ring_ptr++;
  2261. }
  2262. if (pkt->entry_status != 0) {
  2263. qla2x00_error_entry(vha, rsp, (sts_entry_t *) pkt);
  2264. if (qlt_24xx_process_response_error(vha, pkt))
  2265. goto process_err;
  2266. ((response_t *)pkt)->signature = RESPONSE_PROCESSED;
  2267. wmb();
  2268. continue;
  2269. }
  2270. process_err:
  2271. switch (pkt->entry_type) {
  2272. case STATUS_TYPE:
  2273. qla2x00_status_entry(vha, rsp, pkt);
  2274. break;
  2275. case STATUS_CONT_TYPE:
  2276. qla2x00_status_cont_entry(rsp, (sts_cont_entry_t *)pkt);
  2277. break;
  2278. case VP_RPT_ID_IOCB_TYPE:
  2279. qla24xx_report_id_acquisition(vha,
  2280. (struct vp_rpt_id_entry_24xx *)pkt);
  2281. break;
  2282. case LOGINOUT_PORT_IOCB_TYPE:
  2283. qla24xx_logio_entry(vha, rsp->req,
  2284. (struct logio_entry_24xx *)pkt);
  2285. break;
  2286. case CT_IOCB_TYPE:
  2287. qla24xx_els_ct_entry(vha, rsp->req, pkt, CT_IOCB_TYPE);
  2288. break;
  2289. case ELS_IOCB_TYPE:
  2290. qla24xx_els_ct_entry(vha, rsp->req, pkt, ELS_IOCB_TYPE);
  2291. break;
  2292. case ABTS_RECV_24XX:
  2293. if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
  2294. /* ensure that the ATIO queue is empty */
  2295. qlt_handle_abts_recv(vha, (response_t *)pkt);
  2296. break;
  2297. } else {
  2298. /* drop through */
  2299. qlt_24xx_process_atio_queue(vha, 1);
  2300. }
  2301. case ABTS_RESP_24XX:
  2302. case CTIO_TYPE7:
  2303. case NOTIFY_ACK_TYPE:
  2304. case CTIO_CRC2:
  2305. qlt_response_pkt_all_vps(vha, (response_t *)pkt);
  2306. break;
  2307. case MARKER_TYPE:
  2308. /* Do nothing in this case, this check is to prevent it
  2309. * from falling into default case
  2310. */
  2311. break;
  2312. case ABORT_IOCB_TYPE:
  2313. qla24xx_abort_iocb_entry(vha, rsp->req,
  2314. (struct abort_entry_24xx *)pkt);
  2315. break;
  2316. default:
  2317. /* Type Not Supported. */
  2318. ql_dbg(ql_dbg_async, vha, 0x5042,
  2319. "Received unknown response pkt type %x "
  2320. "entry status=%x.\n",
  2321. pkt->entry_type, pkt->entry_status);
  2322. break;
  2323. }
  2324. ((response_t *)pkt)->signature = RESPONSE_PROCESSED;
  2325. wmb();
  2326. }
  2327. /* Adjust ring index */
  2328. if (IS_P3P_TYPE(ha)) {
  2329. struct device_reg_82xx __iomem *reg = &ha->iobase->isp82;
  2330. WRT_REG_DWORD(&reg->rsp_q_out[0], rsp->ring_index);
  2331. } else
  2332. WRT_REG_DWORD(rsp->rsp_q_out, rsp->ring_index);
  2333. }
  2334. static void
  2335. qla2xxx_check_risc_status(scsi_qla_host_t *vha)
  2336. {
  2337. int rval;
  2338. uint32_t cnt;
  2339. struct qla_hw_data *ha = vha->hw;
  2340. struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
  2341. if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha) && !IS_QLA83XX(ha) &&
  2342. !IS_QLA27XX(ha))
  2343. return;
  2344. rval = QLA_SUCCESS;
  2345. WRT_REG_DWORD(&reg->iobase_addr, 0x7C00);
  2346. RD_REG_DWORD(&reg->iobase_addr);
  2347. WRT_REG_DWORD(&reg->iobase_window, 0x0001);
  2348. for (cnt = 10000; (RD_REG_DWORD(&reg->iobase_window) & BIT_0) == 0 &&
  2349. rval == QLA_SUCCESS; cnt--) {
  2350. if (cnt) {
  2351. WRT_REG_DWORD(&reg->iobase_window, 0x0001);
  2352. udelay(10);
  2353. } else
  2354. rval = QLA_FUNCTION_TIMEOUT;
  2355. }
  2356. if (rval == QLA_SUCCESS)
  2357. goto next_test;
  2358. rval = QLA_SUCCESS;
  2359. WRT_REG_DWORD(&reg->iobase_window, 0x0003);
  2360. for (cnt = 100; (RD_REG_DWORD(&reg->iobase_window) & BIT_0) == 0 &&
  2361. rval == QLA_SUCCESS; cnt--) {
  2362. if (cnt) {
  2363. WRT_REG_DWORD(&reg->iobase_window, 0x0003);
  2364. udelay(10);
  2365. } else
  2366. rval = QLA_FUNCTION_TIMEOUT;
  2367. }
  2368. if (rval != QLA_SUCCESS)
  2369. goto done;
  2370. next_test:
  2371. if (RD_REG_DWORD(&reg->iobase_c8) & BIT_3)
  2372. ql_log(ql_log_info, vha, 0x504c,
  2373. "Additional code -- 0x55AA.\n");
  2374. done:
  2375. WRT_REG_DWORD(&reg->iobase_window, 0x0000);
  2376. RD_REG_DWORD(&reg->iobase_window);
  2377. }
  2378. /**
  2379. * qla24xx_intr_handler() - Process interrupts for the ISP23xx and ISP24xx.
  2380. * @irq:
  2381. * @dev_id: SCSI driver HA context
  2382. *
  2383. * Called by system whenever the host adapter generates an interrupt.
  2384. *
  2385. * Returns handled flag.
  2386. */
  2387. irqreturn_t
  2388. qla24xx_intr_handler(int irq, void *dev_id)
  2389. {
  2390. scsi_qla_host_t *vha;
  2391. struct qla_hw_data *ha;
  2392. struct device_reg_24xx __iomem *reg;
  2393. int status;
  2394. unsigned long iter;
  2395. uint32_t stat;
  2396. uint32_t hccr;
  2397. uint16_t mb[8];
  2398. struct rsp_que *rsp;
  2399. unsigned long flags;
  2400. rsp = (struct rsp_que *) dev_id;
  2401. if (!rsp) {
  2402. ql_log(ql_log_info, NULL, 0x5059,
  2403. "%s: NULL response queue pointer.\n", __func__);
  2404. return IRQ_NONE;
  2405. }
  2406. ha = rsp->hw;
  2407. reg = &ha->iobase->isp24;
  2408. status = 0;
  2409. if (unlikely(pci_channel_offline(ha->pdev)))
  2410. return IRQ_HANDLED;
  2411. spin_lock_irqsave(&ha->hardware_lock, flags);
  2412. vha = pci_get_drvdata(ha->pdev);
  2413. for (iter = 50; iter--; ) {
  2414. stat = RD_REG_DWORD(&reg->host_status);
  2415. if (qla2x00_check_reg32_for_disconnect(vha, stat))
  2416. break;
  2417. if (stat & HSRX_RISC_PAUSED) {
  2418. if (unlikely(pci_channel_offline(ha->pdev)))
  2419. break;
  2420. hccr = RD_REG_DWORD(&reg->hccr);
  2421. ql_log(ql_log_warn, vha, 0x504b,
  2422. "RISC paused -- HCCR=%x, Dumping firmware.\n",
  2423. hccr);
  2424. qla2xxx_check_risc_status(vha);
  2425. ha->isp_ops->fw_dump(vha, 1);
  2426. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  2427. break;
  2428. } else if ((stat & HSRX_RISC_INT) == 0)
  2429. break;
  2430. switch (stat & 0xff) {
  2431. case INTR_ROM_MB_SUCCESS:
  2432. case INTR_ROM_MB_FAILED:
  2433. case INTR_MB_SUCCESS:
  2434. case INTR_MB_FAILED:
  2435. qla24xx_mbx_completion(vha, MSW(stat));
  2436. status |= MBX_INTERRUPT;
  2437. break;
  2438. case INTR_ASYNC_EVENT:
  2439. mb[0] = MSW(stat);
  2440. mb[1] = RD_REG_WORD(&reg->mailbox1);
  2441. mb[2] = RD_REG_WORD(&reg->mailbox2);
  2442. mb[3] = RD_REG_WORD(&reg->mailbox3);
  2443. qla2x00_async_event(vha, rsp, mb);
  2444. break;
  2445. case INTR_RSP_QUE_UPDATE:
  2446. case INTR_RSP_QUE_UPDATE_83XX:
  2447. qla24xx_process_response_queue(vha, rsp);
  2448. break;
  2449. case INTR_ATIO_QUE_UPDATE:{
  2450. unsigned long flags2;
  2451. spin_lock_irqsave(&ha->tgt.atio_lock, flags2);
  2452. qlt_24xx_process_atio_queue(vha, 1);
  2453. spin_unlock_irqrestore(&ha->tgt.atio_lock, flags2);
  2454. break;
  2455. }
  2456. case INTR_ATIO_RSP_QUE_UPDATE: {
  2457. unsigned long flags2;
  2458. spin_lock_irqsave(&ha->tgt.atio_lock, flags2);
  2459. qlt_24xx_process_atio_queue(vha, 1);
  2460. spin_unlock_irqrestore(&ha->tgt.atio_lock, flags2);
  2461. qla24xx_process_response_queue(vha, rsp);
  2462. break;
  2463. }
  2464. default:
  2465. ql_dbg(ql_dbg_async, vha, 0x504f,
  2466. "Unrecognized interrupt type (%d).\n", stat * 0xff);
  2467. break;
  2468. }
  2469. WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
  2470. RD_REG_DWORD_RELAXED(&reg->hccr);
  2471. if (unlikely(IS_QLA83XX(ha) && (ha->pdev->revision == 1)))
  2472. ndelay(3500);
  2473. }
  2474. qla2x00_handle_mbx_completion(ha, status);
  2475. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2476. return IRQ_HANDLED;
  2477. }
  2478. static irqreturn_t
  2479. qla24xx_msix_rsp_q(int irq, void *dev_id)
  2480. {
  2481. struct qla_hw_data *ha;
  2482. struct rsp_que *rsp;
  2483. struct device_reg_24xx __iomem *reg;
  2484. struct scsi_qla_host *vha;
  2485. unsigned long flags;
  2486. uint32_t stat = 0;
  2487. rsp = (struct rsp_que *) dev_id;
  2488. if (!rsp) {
  2489. ql_log(ql_log_info, NULL, 0x505a,
  2490. "%s: NULL response queue pointer.\n", __func__);
  2491. return IRQ_NONE;
  2492. }
  2493. ha = rsp->hw;
  2494. reg = &ha->iobase->isp24;
  2495. spin_lock_irqsave(&ha->hardware_lock, flags);
  2496. vha = pci_get_drvdata(ha->pdev);
  2497. /*
  2498. * Use host_status register to check to PCI disconnection before we
  2499. * we process the response queue.
  2500. */
  2501. stat = RD_REG_DWORD(&reg->host_status);
  2502. if (qla2x00_check_reg32_for_disconnect(vha, stat))
  2503. goto out;
  2504. qla24xx_process_response_queue(vha, rsp);
  2505. if (!ha->flags.disable_msix_handshake) {
  2506. WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
  2507. RD_REG_DWORD_RELAXED(&reg->hccr);
  2508. }
  2509. out:
  2510. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2511. return IRQ_HANDLED;
  2512. }
  2513. static irqreturn_t
  2514. qla25xx_msix_rsp_q(int irq, void *dev_id)
  2515. {
  2516. struct qla_hw_data *ha;
  2517. scsi_qla_host_t *vha;
  2518. struct rsp_que *rsp;
  2519. struct device_reg_24xx __iomem *reg;
  2520. unsigned long flags;
  2521. uint32_t hccr = 0;
  2522. rsp = (struct rsp_que *) dev_id;
  2523. if (!rsp) {
  2524. ql_log(ql_log_info, NULL, 0x505b,
  2525. "%s: NULL response queue pointer.\n", __func__);
  2526. return IRQ_NONE;
  2527. }
  2528. ha = rsp->hw;
  2529. vha = pci_get_drvdata(ha->pdev);
  2530. /* Clear the interrupt, if enabled, for this response queue */
  2531. if (!ha->flags.disable_msix_handshake) {
  2532. reg = &ha->iobase->isp24;
  2533. spin_lock_irqsave(&ha->hardware_lock, flags);
  2534. WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
  2535. hccr = RD_REG_DWORD_RELAXED(&reg->hccr);
  2536. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2537. }
  2538. if (qla2x00_check_reg32_for_disconnect(vha, hccr))
  2539. goto out;
  2540. queue_work_on((int) (rsp->id - 1), ha->wq, &rsp->q_work);
  2541. out:
  2542. return IRQ_HANDLED;
  2543. }
  2544. static irqreturn_t
  2545. qla24xx_msix_default(int irq, void *dev_id)
  2546. {
  2547. scsi_qla_host_t *vha;
  2548. struct qla_hw_data *ha;
  2549. struct rsp_que *rsp;
  2550. struct device_reg_24xx __iomem *reg;
  2551. int status;
  2552. uint32_t stat;
  2553. uint32_t hccr;
  2554. uint16_t mb[8];
  2555. unsigned long flags;
  2556. rsp = (struct rsp_que *) dev_id;
  2557. if (!rsp) {
  2558. ql_log(ql_log_info, NULL, 0x505c,
  2559. "%s: NULL response queue pointer.\n", __func__);
  2560. return IRQ_NONE;
  2561. }
  2562. ha = rsp->hw;
  2563. reg = &ha->iobase->isp24;
  2564. status = 0;
  2565. spin_lock_irqsave(&ha->hardware_lock, flags);
  2566. vha = pci_get_drvdata(ha->pdev);
  2567. do {
  2568. stat = RD_REG_DWORD(&reg->host_status);
  2569. if (qla2x00_check_reg32_for_disconnect(vha, stat))
  2570. break;
  2571. if (stat & HSRX_RISC_PAUSED) {
  2572. if (unlikely(pci_channel_offline(ha->pdev)))
  2573. break;
  2574. hccr = RD_REG_DWORD(&reg->hccr);
  2575. ql_log(ql_log_info, vha, 0x5050,
  2576. "RISC paused -- HCCR=%x, Dumping firmware.\n",
  2577. hccr);
  2578. qla2xxx_check_risc_status(vha);
  2579. ha->isp_ops->fw_dump(vha, 1);
  2580. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  2581. break;
  2582. } else if ((stat & HSRX_RISC_INT) == 0)
  2583. break;
  2584. switch (stat & 0xff) {
  2585. case INTR_ROM_MB_SUCCESS:
  2586. case INTR_ROM_MB_FAILED:
  2587. case INTR_MB_SUCCESS:
  2588. case INTR_MB_FAILED:
  2589. qla24xx_mbx_completion(vha, MSW(stat));
  2590. status |= MBX_INTERRUPT;
  2591. break;
  2592. case INTR_ASYNC_EVENT:
  2593. mb[0] = MSW(stat);
  2594. mb[1] = RD_REG_WORD(&reg->mailbox1);
  2595. mb[2] = RD_REG_WORD(&reg->mailbox2);
  2596. mb[3] = RD_REG_WORD(&reg->mailbox3);
  2597. qla2x00_async_event(vha, rsp, mb);
  2598. break;
  2599. case INTR_RSP_QUE_UPDATE:
  2600. case INTR_RSP_QUE_UPDATE_83XX:
  2601. qla24xx_process_response_queue(vha, rsp);
  2602. break;
  2603. case INTR_ATIO_QUE_UPDATE:{
  2604. unsigned long flags2;
  2605. spin_lock_irqsave(&ha->tgt.atio_lock, flags2);
  2606. qlt_24xx_process_atio_queue(vha, 1);
  2607. spin_unlock_irqrestore(&ha->tgt.atio_lock, flags2);
  2608. break;
  2609. }
  2610. case INTR_ATIO_RSP_QUE_UPDATE: {
  2611. unsigned long flags2;
  2612. spin_lock_irqsave(&ha->tgt.atio_lock, flags2);
  2613. qlt_24xx_process_atio_queue(vha, 1);
  2614. spin_unlock_irqrestore(&ha->tgt.atio_lock, flags2);
  2615. qla24xx_process_response_queue(vha, rsp);
  2616. break;
  2617. }
  2618. default:
  2619. ql_dbg(ql_dbg_async, vha, 0x5051,
  2620. "Unrecognized interrupt type (%d).\n", stat & 0xff);
  2621. break;
  2622. }
  2623. WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
  2624. } while (0);
  2625. qla2x00_handle_mbx_completion(ha, status);
  2626. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2627. return IRQ_HANDLED;
  2628. }
  2629. /* Interrupt handling helpers. */
  2630. struct qla_init_msix_entry {
  2631. const char *name;
  2632. irq_handler_t handler;
  2633. };
  2634. static struct qla_init_msix_entry msix_entries[3] = {
  2635. { "qla2xxx (default)", qla24xx_msix_default },
  2636. { "qla2xxx (rsp_q)", qla24xx_msix_rsp_q },
  2637. { "qla2xxx (multiq)", qla25xx_msix_rsp_q },
  2638. };
  2639. static struct qla_init_msix_entry qla82xx_msix_entries[2] = {
  2640. { "qla2xxx (default)", qla82xx_msix_default },
  2641. { "qla2xxx (rsp_q)", qla82xx_msix_rsp_q },
  2642. };
  2643. static struct qla_init_msix_entry qla83xx_msix_entries[3] = {
  2644. { "qla2xxx (default)", qla24xx_msix_default },
  2645. { "qla2xxx (rsp_q)", qla24xx_msix_rsp_q },
  2646. { "qla2xxx (atio_q)", qla83xx_msix_atio_q },
  2647. };
  2648. static void
  2649. qla24xx_disable_msix(struct qla_hw_data *ha)
  2650. {
  2651. int i;
  2652. struct qla_msix_entry *qentry;
  2653. scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
  2654. for (i = 0; i < ha->msix_count; i++) {
  2655. qentry = &ha->msix_entries[i];
  2656. if (qentry->have_irq) {
  2657. /* un-register irq cpu affinity notification */
  2658. irq_set_affinity_notifier(qentry->vector, NULL);
  2659. free_irq(qentry->vector, qentry->rsp);
  2660. }
  2661. }
  2662. pci_disable_msix(ha->pdev);
  2663. kfree(ha->msix_entries);
  2664. ha->msix_entries = NULL;
  2665. ha->flags.msix_enabled = 0;
  2666. ql_dbg(ql_dbg_init, vha, 0x0042,
  2667. "Disabled the MSI.\n");
  2668. }
  2669. static int
  2670. qla24xx_enable_msix(struct qla_hw_data *ha, struct rsp_que *rsp)
  2671. {
  2672. #define MIN_MSIX_COUNT 2
  2673. #define ATIO_VECTOR 2
  2674. int i, ret;
  2675. struct msix_entry *entries;
  2676. struct qla_msix_entry *qentry;
  2677. scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
  2678. entries = kzalloc(sizeof(struct msix_entry) * ha->msix_count,
  2679. GFP_KERNEL);
  2680. if (!entries) {
  2681. ql_log(ql_log_warn, vha, 0x00bc,
  2682. "Failed to allocate memory for msix_entry.\n");
  2683. return -ENOMEM;
  2684. }
  2685. for (i = 0; i < ha->msix_count; i++)
  2686. entries[i].entry = i;
  2687. ret = pci_enable_msix_range(ha->pdev,
  2688. entries, MIN_MSIX_COUNT, ha->msix_count);
  2689. if (ret < 0) {
  2690. ql_log(ql_log_fatal, vha, 0x00c7,
  2691. "MSI-X: Failed to enable support, "
  2692. "giving up -- %d/%d.\n",
  2693. ha->msix_count, ret);
  2694. goto msix_out;
  2695. } else if (ret < ha->msix_count) {
  2696. ql_log(ql_log_warn, vha, 0x00c6,
  2697. "MSI-X: Failed to enable support "
  2698. "-- %d/%d\n Retry with %d vectors.\n",
  2699. ha->msix_count, ret, ret);
  2700. ha->msix_count = ret;
  2701. ha->max_rsp_queues = ha->msix_count - 1;
  2702. }
  2703. ha->msix_entries = kzalloc(sizeof(struct qla_msix_entry) *
  2704. ha->msix_count, GFP_KERNEL);
  2705. if (!ha->msix_entries) {
  2706. ql_log(ql_log_fatal, vha, 0x00c8,
  2707. "Failed to allocate memory for ha->msix_entries.\n");
  2708. ret = -ENOMEM;
  2709. goto msix_out;
  2710. }
  2711. ha->flags.msix_enabled = 1;
  2712. for (i = 0; i < ha->msix_count; i++) {
  2713. qentry = &ha->msix_entries[i];
  2714. qentry->vector = entries[i].vector;
  2715. qentry->entry = entries[i].entry;
  2716. qentry->have_irq = 0;
  2717. qentry->rsp = NULL;
  2718. qentry->irq_notify.notify = qla_irq_affinity_notify;
  2719. qentry->irq_notify.release = qla_irq_affinity_release;
  2720. qentry->cpuid = -1;
  2721. }
  2722. /* Enable MSI-X vectors for the base queue */
  2723. for (i = 0; i < 2; i++) {
  2724. qentry = &ha->msix_entries[i];
  2725. qentry->rsp = rsp;
  2726. rsp->msix = qentry;
  2727. if (IS_P3P_TYPE(ha))
  2728. ret = request_irq(qentry->vector,
  2729. qla82xx_msix_entries[i].handler,
  2730. 0, qla82xx_msix_entries[i].name, rsp);
  2731. else
  2732. ret = request_irq(qentry->vector,
  2733. msix_entries[i].handler,
  2734. 0, msix_entries[i].name, rsp);
  2735. if (ret)
  2736. goto msix_register_fail;
  2737. qentry->have_irq = 1;
  2738. /* Register for CPU affinity notification. */
  2739. irq_set_affinity_notifier(qentry->vector, &qentry->irq_notify);
  2740. /* Schedule work (ie. trigger a notification) to read cpu
  2741. * mask for this specific irq.
  2742. * kref_get is required because
  2743. * irq_affinity_notify() will do
  2744. * kref_put().
  2745. */
  2746. kref_get(&qentry->irq_notify.kref);
  2747. schedule_work(&qentry->irq_notify.work);
  2748. }
  2749. /*
  2750. * If target mode is enable, also request the vector for the ATIO
  2751. * queue.
  2752. */
  2753. if (QLA_TGT_MODE_ENABLED() && IS_ATIO_MSIX_CAPABLE(ha)) {
  2754. qentry = &ha->msix_entries[ATIO_VECTOR];
  2755. qentry->rsp = rsp;
  2756. rsp->msix = qentry;
  2757. ret = request_irq(qentry->vector,
  2758. qla83xx_msix_entries[ATIO_VECTOR].handler,
  2759. 0, qla83xx_msix_entries[ATIO_VECTOR].name, rsp);
  2760. qentry->have_irq = 1;
  2761. }
  2762. msix_register_fail:
  2763. if (ret) {
  2764. ql_log(ql_log_fatal, vha, 0x00cb,
  2765. "MSI-X: unable to register handler -- %x/%d.\n",
  2766. qentry->vector, ret);
  2767. qla24xx_disable_msix(ha);
  2768. ha->mqenable = 0;
  2769. goto msix_out;
  2770. }
  2771. /* Enable MSI-X vector for response queue update for queue 0 */
  2772. if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
  2773. if (ha->msixbase && ha->mqiobase &&
  2774. (ha->max_rsp_queues > 1 || ha->max_req_queues > 1))
  2775. ha->mqenable = 1;
  2776. } else
  2777. if (ha->mqiobase
  2778. && (ha->max_rsp_queues > 1 || ha->max_req_queues > 1))
  2779. ha->mqenable = 1;
  2780. ql_dbg(ql_dbg_multiq, vha, 0xc005,
  2781. "mqiobase=%p, max_rsp_queues=%d, max_req_queues=%d.\n",
  2782. ha->mqiobase, ha->max_rsp_queues, ha->max_req_queues);
  2783. ql_dbg(ql_dbg_init, vha, 0x0055,
  2784. "mqiobase=%p, max_rsp_queues=%d, max_req_queues=%d.\n",
  2785. ha->mqiobase, ha->max_rsp_queues, ha->max_req_queues);
  2786. msix_out:
  2787. kfree(entries);
  2788. return ret;
  2789. }
  2790. int
  2791. qla2x00_request_irqs(struct qla_hw_data *ha, struct rsp_que *rsp)
  2792. {
  2793. int ret = QLA_FUNCTION_FAILED;
  2794. device_reg_t *reg = ha->iobase;
  2795. scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
  2796. /* If possible, enable MSI-X. */
  2797. if (!IS_QLA2432(ha) && !IS_QLA2532(ha) && !IS_QLA8432(ha) &&
  2798. !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha) && !IS_QLAFX00(ha) &&
  2799. !IS_QLA27XX(ha))
  2800. goto skip_msi;
  2801. if (ha->pdev->subsystem_vendor == PCI_VENDOR_ID_HP &&
  2802. (ha->pdev->subsystem_device == 0x7040 ||
  2803. ha->pdev->subsystem_device == 0x7041 ||
  2804. ha->pdev->subsystem_device == 0x1705)) {
  2805. ql_log(ql_log_warn, vha, 0x0034,
  2806. "MSI-X: Unsupported ISP 2432 SSVID/SSDID (0x%X,0x%X).\n",
  2807. ha->pdev->subsystem_vendor,
  2808. ha->pdev->subsystem_device);
  2809. goto skip_msi;
  2810. }
  2811. if (IS_QLA2432(ha) && (ha->pdev->revision < QLA_MSIX_CHIP_REV_24XX)) {
  2812. ql_log(ql_log_warn, vha, 0x0035,
  2813. "MSI-X; Unsupported ISP2432 (0x%X, 0x%X).\n",
  2814. ha->pdev->revision, QLA_MSIX_CHIP_REV_24XX);
  2815. goto skip_msix;
  2816. }
  2817. ret = qla24xx_enable_msix(ha, rsp);
  2818. if (!ret) {
  2819. ql_dbg(ql_dbg_init, vha, 0x0036,
  2820. "MSI-X: Enabled (0x%X, 0x%X).\n",
  2821. ha->chip_revision, ha->fw_attributes);
  2822. goto clear_risc_ints;
  2823. }
  2824. skip_msix:
  2825. ql_log(ql_log_info, vha, 0x0037,
  2826. "Falling back-to MSI mode -%d.\n", ret);
  2827. if (!IS_QLA24XX(ha) && !IS_QLA2532(ha) && !IS_QLA8432(ha) &&
  2828. !IS_QLA8001(ha) && !IS_P3P_TYPE(ha) && !IS_QLAFX00(ha) &&
  2829. !IS_QLA27XX(ha))
  2830. goto skip_msi;
  2831. ret = pci_enable_msi(ha->pdev);
  2832. if (!ret) {
  2833. ql_dbg(ql_dbg_init, vha, 0x0038,
  2834. "MSI: Enabled.\n");
  2835. ha->flags.msi_enabled = 1;
  2836. } else
  2837. ql_log(ql_log_warn, vha, 0x0039,
  2838. "Falling back-to INTa mode -- %d.\n", ret);
  2839. skip_msi:
  2840. /* Skip INTx on ISP82xx. */
  2841. if (!ha->flags.msi_enabled && IS_QLA82XX(ha))
  2842. return QLA_FUNCTION_FAILED;
  2843. ret = request_irq(ha->pdev->irq, ha->isp_ops->intr_handler,
  2844. ha->flags.msi_enabled ? 0 : IRQF_SHARED,
  2845. QLA2XXX_DRIVER_NAME, rsp);
  2846. if (ret) {
  2847. ql_log(ql_log_warn, vha, 0x003a,
  2848. "Failed to reserve interrupt %d already in use.\n",
  2849. ha->pdev->irq);
  2850. goto fail;
  2851. } else if (!ha->flags.msi_enabled) {
  2852. ql_dbg(ql_dbg_init, vha, 0x0125,
  2853. "INTa mode: Enabled.\n");
  2854. ha->flags.mr_intr_valid = 1;
  2855. }
  2856. clear_risc_ints:
  2857. if (IS_FWI2_CAPABLE(ha) || IS_QLAFX00(ha))
  2858. goto fail;
  2859. spin_lock_irq(&ha->hardware_lock);
  2860. WRT_REG_WORD(&reg->isp.semaphore, 0);
  2861. spin_unlock_irq(&ha->hardware_lock);
  2862. fail:
  2863. return ret;
  2864. }
  2865. void
  2866. qla2x00_free_irqs(scsi_qla_host_t *vha)
  2867. {
  2868. struct qla_hw_data *ha = vha->hw;
  2869. struct rsp_que *rsp;
  2870. /*
  2871. * We need to check that ha->rsp_q_map is valid in case we are called
  2872. * from a probe failure context.
  2873. */
  2874. if (!ha->rsp_q_map || !ha->rsp_q_map[0])
  2875. return;
  2876. rsp = ha->rsp_q_map[0];
  2877. if (ha->flags.msix_enabled)
  2878. qla24xx_disable_msix(ha);
  2879. else if (ha->flags.msi_enabled) {
  2880. free_irq(ha->pdev->irq, rsp);
  2881. pci_disable_msi(ha->pdev);
  2882. } else
  2883. free_irq(ha->pdev->irq, rsp);
  2884. }
  2885. int qla25xx_request_irq(struct rsp_que *rsp)
  2886. {
  2887. struct qla_hw_data *ha = rsp->hw;
  2888. struct qla_init_msix_entry *intr = &msix_entries[2];
  2889. struct qla_msix_entry *msix = rsp->msix;
  2890. scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
  2891. int ret;
  2892. ret = request_irq(msix->vector, intr->handler, 0, intr->name, rsp);
  2893. if (ret) {
  2894. ql_log(ql_log_fatal, vha, 0x00e6,
  2895. "MSI-X: Unable to register handler -- %x/%d.\n",
  2896. msix->vector, ret);
  2897. return ret;
  2898. }
  2899. msix->have_irq = 1;
  2900. msix->rsp = rsp;
  2901. return ret;
  2902. }
  2903. /* irq_set_affinity/irqbalance will trigger notification of cpu mask update */
  2904. static void qla_irq_affinity_notify(struct irq_affinity_notify *notify,
  2905. const cpumask_t *mask)
  2906. {
  2907. struct qla_msix_entry *e =
  2908. container_of(notify, struct qla_msix_entry, irq_notify);
  2909. struct qla_hw_data *ha;
  2910. struct scsi_qla_host *base_vha;
  2911. /* user is recommended to set mask to just 1 cpu */
  2912. e->cpuid = cpumask_first(mask);
  2913. ha = e->rsp->hw;
  2914. base_vha = pci_get_drvdata(ha->pdev);
  2915. ql_dbg(ql_dbg_init, base_vha, 0xffff,
  2916. "%s: host %ld : vector %d cpu %d \n", __func__,
  2917. base_vha->host_no, e->vector, e->cpuid);
  2918. if (e->have_irq) {
  2919. if ((IS_QLA83XX(ha) || IS_QLA27XX(ha)) &&
  2920. (e->entry == QLA83XX_RSPQ_MSIX_ENTRY_NUMBER)) {
  2921. ha->tgt.rspq_vector_cpuid = e->cpuid;
  2922. ql_dbg(ql_dbg_init, base_vha, 0xffff,
  2923. "%s: host%ld: rspq vector %d cpu %d runtime change\n",
  2924. __func__, base_vha->host_no, e->vector, e->cpuid);
  2925. }
  2926. }
  2927. }
  2928. static void qla_irq_affinity_release(struct kref *ref)
  2929. {
  2930. struct irq_affinity_notify *notify =
  2931. container_of(ref, struct irq_affinity_notify, kref);
  2932. struct qla_msix_entry *e =
  2933. container_of(notify, struct qla_msix_entry, irq_notify);
  2934. struct scsi_qla_host *base_vha = pci_get_drvdata(e->rsp->hw->pdev);
  2935. ql_dbg(ql_dbg_init, base_vha, 0xffff,
  2936. "%s: host%ld: vector %d cpu %d \n", __func__,
  2937. base_vha->host_no, e->vector, e->cpuid);
  2938. }