slic_ds26522.c 6.5 KB

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  1. /*
  2. * drivers/net/wan/slic_ds26522.c
  3. *
  4. * Copyright (C) 2016 Freescale Semiconductor, Inc.
  5. *
  6. * Author:Zhao Qiang<qiang.zhao@nxp.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of the GNU General Public License as published by the
  10. * Free Software Foundation; either version 2 of the License, or (at your
  11. * option) any later version.
  12. */
  13. #include <linux/bitrev.h>
  14. #include <linux/module.h>
  15. #include <linux/device.h>
  16. #include <linux/kernel.h>
  17. #include <linux/sched.h>
  18. #include <linux/kthread.h>
  19. #include <linux/spi/spi.h>
  20. #include <linux/wait.h>
  21. #include <linux/param.h>
  22. #include <linux/delay.h>
  23. #include <linux/of.h>
  24. #include <linux/of_address.h>
  25. #include <linux/io.h>
  26. #include "slic_ds26522.h"
  27. #define DRV_NAME "ds26522"
  28. #define SLIC_TRANS_LEN 1
  29. #define SLIC_TWO_LEN 2
  30. #define SLIC_THREE_LEN 3
  31. static struct spi_device *g_spi;
  32. MODULE_LICENSE("GPL");
  33. MODULE_AUTHOR("Zhao Qiang<B45475@freescale.com>");
  34. /* the read/write format of address is
  35. * w/r|A13|A12|A11|A10|A9|A8|A7|A6|A5|A4|A3|A2|A1|A0|x
  36. */
  37. static void slic_write(struct spi_device *spi, u16 addr,
  38. u8 data)
  39. {
  40. u8 temp[3];
  41. addr = bitrev16(addr) >> 1;
  42. data = bitrev8(data);
  43. temp[0] = (u8)((addr >> 8) & 0x7f);
  44. temp[1] = (u8)(addr & 0xfe);
  45. temp[2] = data;
  46. /* write spi addr and value */
  47. spi_write(spi, &temp[0], SLIC_THREE_LEN);
  48. }
  49. static u8 slic_read(struct spi_device *spi, u16 addr)
  50. {
  51. u8 temp[2];
  52. u8 data;
  53. addr = bitrev16(addr) >> 1;
  54. temp[0] = (u8)(((addr >> 8) & 0x7f) | 0x80);
  55. temp[1] = (u8)(addr & 0xfe);
  56. spi_write_then_read(spi, &temp[0], SLIC_TWO_LEN, &data,
  57. SLIC_TRANS_LEN);
  58. data = bitrev8(data);
  59. return data;
  60. }
  61. static bool get_slic_product_code(struct spi_device *spi)
  62. {
  63. u8 device_id;
  64. device_id = slic_read(spi, DS26522_IDR_ADDR);
  65. if ((device_id & 0xf8) == 0x68)
  66. return true;
  67. else
  68. return false;
  69. }
  70. static void ds26522_e1_spec_config(struct spi_device *spi)
  71. {
  72. /* Receive E1 Mode, Framer Disabled */
  73. slic_write(spi, DS26522_RMMR_ADDR, DS26522_RMMR_E1);
  74. /* Transmit E1 Mode, Framer Disable */
  75. slic_write(spi, DS26522_TMMR_ADDR, DS26522_TMMR_E1);
  76. /* Receive E1 Mode Framer Enable */
  77. slic_write(spi, DS26522_RMMR_ADDR,
  78. slic_read(spi, DS26522_RMMR_ADDR) | DS26522_RMMR_FRM_EN);
  79. /* Transmit E1 Mode Framer Enable */
  80. slic_write(spi, DS26522_TMMR_ADDR,
  81. slic_read(spi, DS26522_TMMR_ADDR) | DS26522_TMMR_FRM_EN);
  82. /* RCR1, receive E1 B8zs & ESF */
  83. slic_write(spi, DS26522_RCR1_ADDR,
  84. DS26522_RCR1_E1_HDB3 | DS26522_RCR1_E1_CCS);
  85. /* RSYSCLK=2.048MHz, RSYNC-Output */
  86. slic_write(spi, DS26522_RIOCR_ADDR,
  87. DS26522_RIOCR_2048KHZ | DS26522_RIOCR_RSIO_OUT);
  88. /* TCR1 Transmit E1 b8zs */
  89. slic_write(spi, DS26522_TCR1_ADDR, DS26522_TCR1_TB8ZS);
  90. /* TSYSCLK=2.048MHz, TSYNC-Output */
  91. slic_write(spi, DS26522_TIOCR_ADDR,
  92. DS26522_TIOCR_2048KHZ | DS26522_TIOCR_TSIO_OUT);
  93. /* Set E1TAF */
  94. slic_write(spi, DS26522_E1TAF_ADDR, DS26522_E1TAF_DEFAULT);
  95. /* Set E1TNAF register */
  96. slic_write(spi, DS26522_E1TNAF_ADDR, DS26522_E1TNAF_DEFAULT);
  97. /* Receive E1 Mode Framer Enable & init Done */
  98. slic_write(spi, DS26522_RMMR_ADDR, slic_read(spi, DS26522_RMMR_ADDR) |
  99. DS26522_RMMR_INIT_DONE);
  100. /* Transmit E1 Mode Framer Enable & init Done */
  101. slic_write(spi, DS26522_TMMR_ADDR, slic_read(spi, DS26522_TMMR_ADDR) |
  102. DS26522_TMMR_INIT_DONE);
  103. /* Configure LIU E1 mode */
  104. slic_write(spi, DS26522_LTRCR_ADDR, DS26522_LTRCR_E1);
  105. /* E1 Mode default 75 ohm w/Transmit Impedance Matlinking */
  106. slic_write(spi, DS26522_LTITSR_ADDR,
  107. DS26522_LTITSR_TLIS_75OHM | DS26522_LTITSR_LBOS_75OHM);
  108. /* E1 Mode default 75 ohm Long Haul w/Receive Impedance Matlinking */
  109. slic_write(spi, DS26522_LRISMR_ADDR,
  110. DS26522_LRISMR_75OHM | DS26522_LRISMR_MAX);
  111. /* Enable Transmit output */
  112. slic_write(spi, DS26522_LMCR_ADDR, DS26522_LMCR_TE);
  113. }
  114. static int slic_ds26522_init_configure(struct spi_device *spi)
  115. {
  116. u16 addr;
  117. /* set clock */
  118. slic_write(spi, DS26522_GTCCR_ADDR, DS26522_GTCCR_BPREFSEL_REFCLKIN |
  119. DS26522_GTCCR_BFREQSEL_2048KHZ |
  120. DS26522_GTCCR_FREQSEL_2048KHZ);
  121. slic_write(spi, DS26522_GTCR2_ADDR, DS26522_GTCR2_TSSYNCOUT);
  122. slic_write(spi, DS26522_GFCR_ADDR, DS26522_GFCR_BPCLK_2048KHZ);
  123. /* set gtcr */
  124. slic_write(spi, DS26522_GTCR1_ADDR, DS26522_GTCR1);
  125. /* Global LIU Software Reset Register */
  126. slic_write(spi, DS26522_GLSRR_ADDR, DS26522_GLSRR_RESET);
  127. /* Global Framer and BERT Software Reset Register */
  128. slic_write(spi, DS26522_GFSRR_ADDR, DS26522_GFSRR_RESET);
  129. usleep_range(100, 120);
  130. slic_write(spi, DS26522_GLSRR_ADDR, DS26522_GLSRR_NORMAL);
  131. slic_write(spi, DS26522_GFSRR_ADDR, DS26522_GFSRR_NORMAL);
  132. /* Perform RX/TX SRESET,Reset receiver */
  133. slic_write(spi, DS26522_RMMR_ADDR, DS26522_RMMR_SFTRST);
  134. /* Reset tranceiver */
  135. slic_write(spi, DS26522_TMMR_ADDR, DS26522_TMMR_SFTRST);
  136. usleep_range(100, 120);
  137. /* Zero all Framer Registers */
  138. for (addr = DS26522_RF_ADDR_START; addr <= DS26522_RF_ADDR_END;
  139. addr++)
  140. slic_write(spi, addr, 0);
  141. for (addr = DS26522_TF_ADDR_START; addr <= DS26522_TF_ADDR_END;
  142. addr++)
  143. slic_write(spi, addr, 0);
  144. for (addr = DS26522_LIU_ADDR_START; addr <= DS26522_LIU_ADDR_END;
  145. addr++)
  146. slic_write(spi, addr, 0);
  147. for (addr = DS26522_BERT_ADDR_START; addr <= DS26522_BERT_ADDR_END;
  148. addr++)
  149. slic_write(spi, addr, 0);
  150. /* setup ds26522 for E1 specification */
  151. ds26522_e1_spec_config(spi);
  152. slic_write(spi, DS26522_GTCR1_ADDR, 0x00);
  153. return 0;
  154. }
  155. static int slic_ds26522_remove(struct spi_device *spi)
  156. {
  157. pr_info("DS26522 module uninstalled\n");
  158. return 0;
  159. }
  160. static int slic_ds26522_probe(struct spi_device *spi)
  161. {
  162. int ret = 0;
  163. g_spi = spi;
  164. spi->bits_per_word = 8;
  165. if (!get_slic_product_code(spi))
  166. return ret;
  167. ret = slic_ds26522_init_configure(spi);
  168. if (ret == 0)
  169. pr_info("DS26522 cs%d configurated\n", spi->chip_select);
  170. return ret;
  171. }
  172. static const struct spi_device_id slic_ds26522_id[] = {
  173. { .name = "ds26522" },
  174. { /* sentinel */ },
  175. };
  176. MODULE_DEVICE_TABLE(spi, slic_ds26522_id);
  177. static const struct of_device_id slic_ds26522_match[] = {
  178. {
  179. .compatible = "maxim,ds26522",
  180. },
  181. {},
  182. };
  183. MODULE_DEVICE_TABLE(of, slic_ds26522_match);
  184. static struct spi_driver slic_ds26522_driver = {
  185. .driver = {
  186. .name = "ds26522",
  187. .bus = &spi_bus_type,
  188. .owner = THIS_MODULE,
  189. .of_match_table = slic_ds26522_match,
  190. },
  191. .probe = slic_ds26522_probe,
  192. .remove = slic_ds26522_remove,
  193. .id_table = slic_ds26522_id,
  194. };
  195. static int __init slic_ds26522_init(void)
  196. {
  197. return spi_register_driver(&slic_ds26522_driver);
  198. }
  199. static void __exit slic_ds26522_exit(void)
  200. {
  201. spi_unregister_driver(&slic_ds26522_driver);
  202. }
  203. module_init(slic_ds26522_init);
  204. module_exit(slic_ds26522_exit);