fjes_hw.c 26 KB

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  1. /*
  2. * FUJITSU Extended Socket Network Device driver
  3. * Copyright (c) 2015 FUJITSU LIMITED
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms and conditions of the GNU General Public License,
  7. * version 2, as published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program; if not, see <http://www.gnu.org/licenses/>.
  16. *
  17. * The full GNU General Public License is included in this distribution in
  18. * the file called "COPYING".
  19. *
  20. */
  21. #include "fjes_hw.h"
  22. #include "fjes.h"
  23. static void fjes_hw_update_zone_task(struct work_struct *);
  24. static void fjes_hw_epstop_task(struct work_struct *);
  25. /* supported MTU list */
  26. const u32 fjes_support_mtu[] = {
  27. FJES_MTU_DEFINE(8 * 1024),
  28. FJES_MTU_DEFINE(16 * 1024),
  29. FJES_MTU_DEFINE(32 * 1024),
  30. FJES_MTU_DEFINE(64 * 1024),
  31. 0
  32. };
  33. u32 fjes_hw_rd32(struct fjes_hw *hw, u32 reg)
  34. {
  35. u8 *base = hw->base;
  36. u32 value = 0;
  37. value = readl(&base[reg]);
  38. return value;
  39. }
  40. static u8 *fjes_hw_iomap(struct fjes_hw *hw)
  41. {
  42. u8 *base;
  43. if (!request_mem_region(hw->hw_res.start, hw->hw_res.size,
  44. fjes_driver_name)) {
  45. pr_err("request_mem_region failed\n");
  46. return NULL;
  47. }
  48. base = (u8 *)ioremap_nocache(hw->hw_res.start, hw->hw_res.size);
  49. return base;
  50. }
  51. static void fjes_hw_iounmap(struct fjes_hw *hw)
  52. {
  53. iounmap(hw->base);
  54. release_mem_region(hw->hw_res.start, hw->hw_res.size);
  55. }
  56. int fjes_hw_reset(struct fjes_hw *hw)
  57. {
  58. union REG_DCTL dctl;
  59. int timeout;
  60. dctl.reg = 0;
  61. dctl.bits.reset = 1;
  62. wr32(XSCT_DCTL, dctl.reg);
  63. timeout = FJES_DEVICE_RESET_TIMEOUT * 1000;
  64. dctl.reg = rd32(XSCT_DCTL);
  65. while ((dctl.bits.reset == 1) && (timeout > 0)) {
  66. msleep(1000);
  67. dctl.reg = rd32(XSCT_DCTL);
  68. timeout -= 1000;
  69. }
  70. return timeout > 0 ? 0 : -EIO;
  71. }
  72. static int fjes_hw_get_max_epid(struct fjes_hw *hw)
  73. {
  74. union REG_MAX_EP info;
  75. info.reg = rd32(XSCT_MAX_EP);
  76. return info.bits.maxep;
  77. }
  78. static int fjes_hw_get_my_epid(struct fjes_hw *hw)
  79. {
  80. union REG_OWNER_EPID info;
  81. info.reg = rd32(XSCT_OWNER_EPID);
  82. return info.bits.epid;
  83. }
  84. static int fjes_hw_alloc_shared_status_region(struct fjes_hw *hw)
  85. {
  86. size_t size;
  87. size = sizeof(struct fjes_device_shared_info) +
  88. (sizeof(u8) * hw->max_epid);
  89. hw->hw_info.share = kzalloc(size, GFP_KERNEL);
  90. if (!hw->hw_info.share)
  91. return -ENOMEM;
  92. hw->hw_info.share->epnum = hw->max_epid;
  93. return 0;
  94. }
  95. static void fjes_hw_free_shared_status_region(struct fjes_hw *hw)
  96. {
  97. kfree(hw->hw_info.share);
  98. hw->hw_info.share = NULL;
  99. }
  100. static int fjes_hw_alloc_epbuf(struct epbuf_handler *epbh)
  101. {
  102. void *mem;
  103. mem = vzalloc(EP_BUFFER_SIZE);
  104. if (!mem)
  105. return -ENOMEM;
  106. epbh->buffer = mem;
  107. epbh->size = EP_BUFFER_SIZE;
  108. epbh->info = (union ep_buffer_info *)mem;
  109. epbh->ring = (u8 *)(mem + sizeof(union ep_buffer_info));
  110. return 0;
  111. }
  112. static void fjes_hw_free_epbuf(struct epbuf_handler *epbh)
  113. {
  114. vfree(epbh->buffer);
  115. epbh->buffer = NULL;
  116. epbh->size = 0;
  117. epbh->info = NULL;
  118. epbh->ring = NULL;
  119. }
  120. void fjes_hw_setup_epbuf(struct epbuf_handler *epbh, u8 *mac_addr, u32 mtu)
  121. {
  122. union ep_buffer_info *info = epbh->info;
  123. u16 vlan_id[EP_BUFFER_SUPPORT_VLAN_MAX];
  124. int i;
  125. for (i = 0; i < EP_BUFFER_SUPPORT_VLAN_MAX; i++)
  126. vlan_id[i] = info->v1i.vlan_id[i];
  127. memset(info, 0, sizeof(union ep_buffer_info));
  128. info->v1i.version = 0; /* version 0 */
  129. for (i = 0; i < ETH_ALEN; i++)
  130. info->v1i.mac_addr[i] = mac_addr[i];
  131. info->v1i.head = 0;
  132. info->v1i.tail = 1;
  133. info->v1i.info_size = sizeof(union ep_buffer_info);
  134. info->v1i.buffer_size = epbh->size - info->v1i.info_size;
  135. info->v1i.frame_max = FJES_MTU_TO_FRAME_SIZE(mtu);
  136. info->v1i.count_max =
  137. EP_RING_NUM(info->v1i.buffer_size, info->v1i.frame_max);
  138. for (i = 0; i < EP_BUFFER_SUPPORT_VLAN_MAX; i++)
  139. info->v1i.vlan_id[i] = vlan_id[i];
  140. info->v1i.rx_status |= FJES_RX_MTU_CHANGING_DONE;
  141. }
  142. void
  143. fjes_hw_init_command_registers(struct fjes_hw *hw,
  144. struct fjes_device_command_param *param)
  145. {
  146. /* Request Buffer length */
  147. wr32(XSCT_REQBL, (__le32)(param->req_len));
  148. /* Response Buffer Length */
  149. wr32(XSCT_RESPBL, (__le32)(param->res_len));
  150. /* Request Buffer Address */
  151. wr32(XSCT_REQBAL,
  152. (__le32)(param->req_start & GENMASK_ULL(31, 0)));
  153. wr32(XSCT_REQBAH,
  154. (__le32)((param->req_start & GENMASK_ULL(63, 32)) >> 32));
  155. /* Response Buffer Address */
  156. wr32(XSCT_RESPBAL,
  157. (__le32)(param->res_start & GENMASK_ULL(31, 0)));
  158. wr32(XSCT_RESPBAH,
  159. (__le32)((param->res_start & GENMASK_ULL(63, 32)) >> 32));
  160. /* Share status address */
  161. wr32(XSCT_SHSTSAL,
  162. (__le32)(param->share_start & GENMASK_ULL(31, 0)));
  163. wr32(XSCT_SHSTSAH,
  164. (__le32)((param->share_start & GENMASK_ULL(63, 32)) >> 32));
  165. }
  166. static int fjes_hw_setup(struct fjes_hw *hw)
  167. {
  168. u8 mac[ETH_ALEN] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
  169. struct fjes_device_command_param param;
  170. struct ep_share_mem_info *buf_pair;
  171. unsigned long flags;
  172. size_t mem_size;
  173. int result;
  174. int epidx;
  175. void *buf;
  176. hw->hw_info.max_epid = &hw->max_epid;
  177. hw->hw_info.my_epid = &hw->my_epid;
  178. buf = kcalloc(hw->max_epid, sizeof(struct ep_share_mem_info),
  179. GFP_KERNEL);
  180. if (!buf)
  181. return -ENOMEM;
  182. hw->ep_shm_info = (struct ep_share_mem_info *)buf;
  183. mem_size = FJES_DEV_REQ_BUF_SIZE(hw->max_epid);
  184. hw->hw_info.req_buf = kzalloc(mem_size, GFP_KERNEL);
  185. if (!(hw->hw_info.req_buf))
  186. return -ENOMEM;
  187. hw->hw_info.req_buf_size = mem_size;
  188. mem_size = FJES_DEV_RES_BUF_SIZE(hw->max_epid);
  189. hw->hw_info.res_buf = kzalloc(mem_size, GFP_KERNEL);
  190. if (!(hw->hw_info.res_buf))
  191. return -ENOMEM;
  192. hw->hw_info.res_buf_size = mem_size;
  193. result = fjes_hw_alloc_shared_status_region(hw);
  194. if (result)
  195. return result;
  196. hw->hw_info.buffer_share_bit = 0;
  197. hw->hw_info.buffer_unshare_reserve_bit = 0;
  198. for (epidx = 0; epidx < hw->max_epid; epidx++) {
  199. if (epidx != hw->my_epid) {
  200. buf_pair = &hw->ep_shm_info[epidx];
  201. result = fjes_hw_alloc_epbuf(&buf_pair->tx);
  202. if (result)
  203. return result;
  204. result = fjes_hw_alloc_epbuf(&buf_pair->rx);
  205. if (result)
  206. return result;
  207. spin_lock_irqsave(&hw->rx_status_lock, flags);
  208. fjes_hw_setup_epbuf(&buf_pair->tx, mac,
  209. fjes_support_mtu[0]);
  210. fjes_hw_setup_epbuf(&buf_pair->rx, mac,
  211. fjes_support_mtu[0]);
  212. spin_unlock_irqrestore(&hw->rx_status_lock, flags);
  213. }
  214. }
  215. memset(&param, 0, sizeof(param));
  216. param.req_len = hw->hw_info.req_buf_size;
  217. param.req_start = __pa(hw->hw_info.req_buf);
  218. param.res_len = hw->hw_info.res_buf_size;
  219. param.res_start = __pa(hw->hw_info.res_buf);
  220. param.share_start = __pa(hw->hw_info.share->ep_status);
  221. fjes_hw_init_command_registers(hw, &param);
  222. return 0;
  223. }
  224. static void fjes_hw_cleanup(struct fjes_hw *hw)
  225. {
  226. int epidx;
  227. if (!hw->ep_shm_info)
  228. return;
  229. fjes_hw_free_shared_status_region(hw);
  230. kfree(hw->hw_info.req_buf);
  231. hw->hw_info.req_buf = NULL;
  232. kfree(hw->hw_info.res_buf);
  233. hw->hw_info.res_buf = NULL;
  234. for (epidx = 0; epidx < hw->max_epid ; epidx++) {
  235. if (epidx == hw->my_epid)
  236. continue;
  237. fjes_hw_free_epbuf(&hw->ep_shm_info[epidx].tx);
  238. fjes_hw_free_epbuf(&hw->ep_shm_info[epidx].rx);
  239. }
  240. kfree(hw->ep_shm_info);
  241. hw->ep_shm_info = NULL;
  242. }
  243. int fjes_hw_init(struct fjes_hw *hw)
  244. {
  245. int ret;
  246. hw->base = fjes_hw_iomap(hw);
  247. if (!hw->base)
  248. return -EIO;
  249. ret = fjes_hw_reset(hw);
  250. if (ret)
  251. return ret;
  252. fjes_hw_set_irqmask(hw, REG_ICTL_MASK_ALL, true);
  253. INIT_WORK(&hw->update_zone_task, fjes_hw_update_zone_task);
  254. INIT_WORK(&hw->epstop_task, fjes_hw_epstop_task);
  255. mutex_init(&hw->hw_info.lock);
  256. spin_lock_init(&hw->rx_status_lock);
  257. hw->max_epid = fjes_hw_get_max_epid(hw);
  258. hw->my_epid = fjes_hw_get_my_epid(hw);
  259. if ((hw->max_epid == 0) || (hw->my_epid >= hw->max_epid))
  260. return -ENXIO;
  261. ret = fjes_hw_setup(hw);
  262. return ret;
  263. }
  264. void fjes_hw_exit(struct fjes_hw *hw)
  265. {
  266. int ret;
  267. if (hw->base) {
  268. ret = fjes_hw_reset(hw);
  269. if (ret)
  270. pr_err("%s: reset error", __func__);
  271. fjes_hw_iounmap(hw);
  272. hw->base = NULL;
  273. }
  274. fjes_hw_cleanup(hw);
  275. cancel_work_sync(&hw->update_zone_task);
  276. cancel_work_sync(&hw->epstop_task);
  277. }
  278. static enum fjes_dev_command_response_e
  279. fjes_hw_issue_request_command(struct fjes_hw *hw,
  280. enum fjes_dev_command_request_type type)
  281. {
  282. enum fjes_dev_command_response_e ret = FJES_CMD_STATUS_UNKNOWN;
  283. union REG_CR cr;
  284. union REG_CS cs;
  285. int timeout;
  286. cr.reg = 0;
  287. cr.bits.req_start = 1;
  288. cr.bits.req_code = type;
  289. wr32(XSCT_CR, cr.reg);
  290. cr.reg = rd32(XSCT_CR);
  291. if (cr.bits.error == 0) {
  292. timeout = FJES_COMMAND_REQ_TIMEOUT * 1000;
  293. cs.reg = rd32(XSCT_CS);
  294. while ((cs.bits.complete != 1) && timeout > 0) {
  295. msleep(1000);
  296. cs.reg = rd32(XSCT_CS);
  297. timeout -= 1000;
  298. }
  299. if (cs.bits.complete == 1)
  300. ret = FJES_CMD_STATUS_NORMAL;
  301. else if (timeout <= 0)
  302. ret = FJES_CMD_STATUS_TIMEOUT;
  303. } else {
  304. switch (cr.bits.err_info) {
  305. case FJES_CMD_REQ_ERR_INFO_PARAM:
  306. ret = FJES_CMD_STATUS_ERROR_PARAM;
  307. break;
  308. case FJES_CMD_REQ_ERR_INFO_STATUS:
  309. ret = FJES_CMD_STATUS_ERROR_STATUS;
  310. break;
  311. default:
  312. ret = FJES_CMD_STATUS_UNKNOWN;
  313. break;
  314. }
  315. }
  316. return ret;
  317. }
  318. int fjes_hw_request_info(struct fjes_hw *hw)
  319. {
  320. union fjes_device_command_req *req_buf = hw->hw_info.req_buf;
  321. union fjes_device_command_res *res_buf = hw->hw_info.res_buf;
  322. enum fjes_dev_command_response_e ret;
  323. int result;
  324. memset(req_buf, 0, hw->hw_info.req_buf_size);
  325. memset(res_buf, 0, hw->hw_info.res_buf_size);
  326. req_buf->info.length = FJES_DEV_COMMAND_INFO_REQ_LEN;
  327. res_buf->info.length = 0;
  328. res_buf->info.code = 0;
  329. ret = fjes_hw_issue_request_command(hw, FJES_CMD_REQ_INFO);
  330. result = 0;
  331. if (FJES_DEV_COMMAND_INFO_RES_LEN((*hw->hw_info.max_epid)) !=
  332. res_buf->info.length) {
  333. result = -ENOMSG;
  334. } else if (ret == FJES_CMD_STATUS_NORMAL) {
  335. switch (res_buf->info.code) {
  336. case FJES_CMD_REQ_RES_CODE_NORMAL:
  337. result = 0;
  338. break;
  339. default:
  340. result = -EPERM;
  341. break;
  342. }
  343. } else {
  344. switch (ret) {
  345. case FJES_CMD_STATUS_UNKNOWN:
  346. result = -EPERM;
  347. break;
  348. case FJES_CMD_STATUS_TIMEOUT:
  349. result = -EBUSY;
  350. break;
  351. case FJES_CMD_STATUS_ERROR_PARAM:
  352. result = -EPERM;
  353. break;
  354. case FJES_CMD_STATUS_ERROR_STATUS:
  355. result = -EPERM;
  356. break;
  357. default:
  358. result = -EPERM;
  359. break;
  360. }
  361. }
  362. return result;
  363. }
  364. int fjes_hw_register_buff_addr(struct fjes_hw *hw, int dest_epid,
  365. struct ep_share_mem_info *buf_pair)
  366. {
  367. union fjes_device_command_req *req_buf = hw->hw_info.req_buf;
  368. union fjes_device_command_res *res_buf = hw->hw_info.res_buf;
  369. enum fjes_dev_command_response_e ret;
  370. int page_count;
  371. int timeout;
  372. int i, idx;
  373. void *addr;
  374. int result;
  375. if (test_bit(dest_epid, &hw->hw_info.buffer_share_bit))
  376. return 0;
  377. memset(req_buf, 0, hw->hw_info.req_buf_size);
  378. memset(res_buf, 0, hw->hw_info.res_buf_size);
  379. req_buf->share_buffer.length = FJES_DEV_COMMAND_SHARE_BUFFER_REQ_LEN(
  380. buf_pair->tx.size,
  381. buf_pair->rx.size);
  382. req_buf->share_buffer.epid = dest_epid;
  383. idx = 0;
  384. req_buf->share_buffer.buffer[idx++] = buf_pair->tx.size;
  385. page_count = buf_pair->tx.size / EP_BUFFER_INFO_SIZE;
  386. for (i = 0; i < page_count; i++) {
  387. addr = ((u8 *)(buf_pair->tx.buffer)) +
  388. (i * EP_BUFFER_INFO_SIZE);
  389. req_buf->share_buffer.buffer[idx++] =
  390. (__le64)(page_to_phys(vmalloc_to_page(addr)) +
  391. offset_in_page(addr));
  392. }
  393. req_buf->share_buffer.buffer[idx++] = buf_pair->rx.size;
  394. page_count = buf_pair->rx.size / EP_BUFFER_INFO_SIZE;
  395. for (i = 0; i < page_count; i++) {
  396. addr = ((u8 *)(buf_pair->rx.buffer)) +
  397. (i * EP_BUFFER_INFO_SIZE);
  398. req_buf->share_buffer.buffer[idx++] =
  399. (__le64)(page_to_phys(vmalloc_to_page(addr)) +
  400. offset_in_page(addr));
  401. }
  402. res_buf->share_buffer.length = 0;
  403. res_buf->share_buffer.code = 0;
  404. ret = fjes_hw_issue_request_command(hw, FJES_CMD_REQ_SHARE_BUFFER);
  405. timeout = FJES_COMMAND_REQ_BUFF_TIMEOUT * 1000;
  406. while ((ret == FJES_CMD_STATUS_NORMAL) &&
  407. (res_buf->share_buffer.length ==
  408. FJES_DEV_COMMAND_SHARE_BUFFER_RES_LEN) &&
  409. (res_buf->share_buffer.code == FJES_CMD_REQ_RES_CODE_BUSY) &&
  410. (timeout > 0)) {
  411. msleep(200 + hw->my_epid * 20);
  412. timeout -= (200 + hw->my_epid * 20);
  413. res_buf->share_buffer.length = 0;
  414. res_buf->share_buffer.code = 0;
  415. ret = fjes_hw_issue_request_command(
  416. hw, FJES_CMD_REQ_SHARE_BUFFER);
  417. }
  418. result = 0;
  419. if (res_buf->share_buffer.length !=
  420. FJES_DEV_COMMAND_SHARE_BUFFER_RES_LEN)
  421. result = -ENOMSG;
  422. else if (ret == FJES_CMD_STATUS_NORMAL) {
  423. switch (res_buf->share_buffer.code) {
  424. case FJES_CMD_REQ_RES_CODE_NORMAL:
  425. result = 0;
  426. set_bit(dest_epid, &hw->hw_info.buffer_share_bit);
  427. break;
  428. case FJES_CMD_REQ_RES_CODE_BUSY:
  429. result = -EBUSY;
  430. break;
  431. default:
  432. result = -EPERM;
  433. break;
  434. }
  435. } else {
  436. switch (ret) {
  437. case FJES_CMD_STATUS_UNKNOWN:
  438. result = -EPERM;
  439. break;
  440. case FJES_CMD_STATUS_TIMEOUT:
  441. result = -EBUSY;
  442. break;
  443. case FJES_CMD_STATUS_ERROR_PARAM:
  444. case FJES_CMD_STATUS_ERROR_STATUS:
  445. default:
  446. result = -EPERM;
  447. break;
  448. }
  449. }
  450. return result;
  451. }
  452. int fjes_hw_unregister_buff_addr(struct fjes_hw *hw, int dest_epid)
  453. {
  454. union fjes_device_command_req *req_buf = hw->hw_info.req_buf;
  455. union fjes_device_command_res *res_buf = hw->hw_info.res_buf;
  456. struct fjes_device_shared_info *share = hw->hw_info.share;
  457. enum fjes_dev_command_response_e ret;
  458. int timeout;
  459. int result;
  460. if (!hw->base)
  461. return -EPERM;
  462. if (!req_buf || !res_buf || !share)
  463. return -EPERM;
  464. if (!test_bit(dest_epid, &hw->hw_info.buffer_share_bit))
  465. return 0;
  466. memset(req_buf, 0, hw->hw_info.req_buf_size);
  467. memset(res_buf, 0, hw->hw_info.res_buf_size);
  468. req_buf->unshare_buffer.length =
  469. FJES_DEV_COMMAND_UNSHARE_BUFFER_REQ_LEN;
  470. req_buf->unshare_buffer.epid = dest_epid;
  471. res_buf->unshare_buffer.length = 0;
  472. res_buf->unshare_buffer.code = 0;
  473. ret = fjes_hw_issue_request_command(hw, FJES_CMD_REQ_UNSHARE_BUFFER);
  474. timeout = FJES_COMMAND_REQ_BUFF_TIMEOUT * 1000;
  475. while ((ret == FJES_CMD_STATUS_NORMAL) &&
  476. (res_buf->unshare_buffer.length ==
  477. FJES_DEV_COMMAND_UNSHARE_BUFFER_RES_LEN) &&
  478. (res_buf->unshare_buffer.code ==
  479. FJES_CMD_REQ_RES_CODE_BUSY) &&
  480. (timeout > 0)) {
  481. msleep(200 + hw->my_epid * 20);
  482. timeout -= (200 + hw->my_epid * 20);
  483. res_buf->unshare_buffer.length = 0;
  484. res_buf->unshare_buffer.code = 0;
  485. ret =
  486. fjes_hw_issue_request_command(hw, FJES_CMD_REQ_UNSHARE_BUFFER);
  487. }
  488. result = 0;
  489. if (res_buf->unshare_buffer.length !=
  490. FJES_DEV_COMMAND_UNSHARE_BUFFER_RES_LEN) {
  491. result = -ENOMSG;
  492. } else if (ret == FJES_CMD_STATUS_NORMAL) {
  493. switch (res_buf->unshare_buffer.code) {
  494. case FJES_CMD_REQ_RES_CODE_NORMAL:
  495. result = 0;
  496. clear_bit(dest_epid, &hw->hw_info.buffer_share_bit);
  497. break;
  498. case FJES_CMD_REQ_RES_CODE_BUSY:
  499. result = -EBUSY;
  500. break;
  501. default:
  502. result = -EPERM;
  503. break;
  504. }
  505. } else {
  506. switch (ret) {
  507. case FJES_CMD_STATUS_UNKNOWN:
  508. result = -EPERM;
  509. break;
  510. case FJES_CMD_STATUS_TIMEOUT:
  511. result = -EBUSY;
  512. break;
  513. case FJES_CMD_STATUS_ERROR_PARAM:
  514. case FJES_CMD_STATUS_ERROR_STATUS:
  515. default:
  516. result = -EPERM;
  517. break;
  518. }
  519. }
  520. return result;
  521. }
  522. int fjes_hw_raise_interrupt(struct fjes_hw *hw, int dest_epid,
  523. enum REG_ICTL_MASK mask)
  524. {
  525. u32 ig = mask | dest_epid;
  526. wr32(XSCT_IG, cpu_to_le32(ig));
  527. return 0;
  528. }
  529. u32 fjes_hw_capture_interrupt_status(struct fjes_hw *hw)
  530. {
  531. u32 cur_is;
  532. cur_is = rd32(XSCT_IS);
  533. return cur_is;
  534. }
  535. void fjes_hw_set_irqmask(struct fjes_hw *hw,
  536. enum REG_ICTL_MASK intr_mask, bool mask)
  537. {
  538. if (mask)
  539. wr32(XSCT_IMS, intr_mask);
  540. else
  541. wr32(XSCT_IMC, intr_mask);
  542. }
  543. bool fjes_hw_epid_is_same_zone(struct fjes_hw *hw, int epid)
  544. {
  545. if (epid >= hw->max_epid)
  546. return false;
  547. if ((hw->ep_shm_info[epid].es_status !=
  548. FJES_ZONING_STATUS_ENABLE) ||
  549. (hw->ep_shm_info[hw->my_epid].zone ==
  550. FJES_ZONING_ZONE_TYPE_NONE))
  551. return false;
  552. else
  553. return (hw->ep_shm_info[epid].zone ==
  554. hw->ep_shm_info[hw->my_epid].zone);
  555. }
  556. int fjes_hw_epid_is_shared(struct fjes_device_shared_info *share,
  557. int dest_epid)
  558. {
  559. int value = false;
  560. if (dest_epid < share->epnum)
  561. value = share->ep_status[dest_epid];
  562. return value;
  563. }
  564. static bool fjes_hw_epid_is_stop_requested(struct fjes_hw *hw, int src_epid)
  565. {
  566. return test_bit(src_epid, &hw->txrx_stop_req_bit);
  567. }
  568. static bool fjes_hw_epid_is_stop_process_done(struct fjes_hw *hw, int src_epid)
  569. {
  570. return (hw->ep_shm_info[src_epid].tx.info->v1i.rx_status &
  571. FJES_RX_STOP_REQ_DONE);
  572. }
  573. enum ep_partner_status
  574. fjes_hw_get_partner_ep_status(struct fjes_hw *hw, int epid)
  575. {
  576. enum ep_partner_status status;
  577. if (fjes_hw_epid_is_shared(hw->hw_info.share, epid)) {
  578. if (fjes_hw_epid_is_stop_requested(hw, epid)) {
  579. status = EP_PARTNER_WAITING;
  580. } else {
  581. if (fjes_hw_epid_is_stop_process_done(hw, epid))
  582. status = EP_PARTNER_COMPLETE;
  583. else
  584. status = EP_PARTNER_SHARED;
  585. }
  586. } else {
  587. status = EP_PARTNER_UNSHARE;
  588. }
  589. return status;
  590. }
  591. void fjes_hw_raise_epstop(struct fjes_hw *hw)
  592. {
  593. enum ep_partner_status status;
  594. unsigned long flags;
  595. int epidx;
  596. for (epidx = 0; epidx < hw->max_epid; epidx++) {
  597. if (epidx == hw->my_epid)
  598. continue;
  599. status = fjes_hw_get_partner_ep_status(hw, epidx);
  600. switch (status) {
  601. case EP_PARTNER_SHARED:
  602. fjes_hw_raise_interrupt(hw, epidx,
  603. REG_ICTL_MASK_TXRX_STOP_REQ);
  604. break;
  605. default:
  606. break;
  607. }
  608. set_bit(epidx, &hw->hw_info.buffer_unshare_reserve_bit);
  609. set_bit(epidx, &hw->txrx_stop_req_bit);
  610. spin_lock_irqsave(&hw->rx_status_lock, flags);
  611. hw->ep_shm_info[epidx].tx.info->v1i.rx_status |=
  612. FJES_RX_STOP_REQ_REQUEST;
  613. spin_unlock_irqrestore(&hw->rx_status_lock, flags);
  614. }
  615. }
  616. int fjes_hw_wait_epstop(struct fjes_hw *hw)
  617. {
  618. enum ep_partner_status status;
  619. union ep_buffer_info *info;
  620. int wait_time = 0;
  621. int epidx;
  622. while (hw->hw_info.buffer_unshare_reserve_bit &&
  623. (wait_time < FJES_COMMAND_EPSTOP_WAIT_TIMEOUT * 1000)) {
  624. for (epidx = 0; epidx < hw->max_epid; epidx++) {
  625. if (epidx == hw->my_epid)
  626. continue;
  627. status = fjes_hw_epid_is_shared(hw->hw_info.share,
  628. epidx);
  629. info = hw->ep_shm_info[epidx].rx.info;
  630. if ((!status ||
  631. (info->v1i.rx_status &
  632. FJES_RX_STOP_REQ_DONE)) &&
  633. test_bit(epidx,
  634. &hw->hw_info.buffer_unshare_reserve_bit)) {
  635. clear_bit(epidx,
  636. &hw->hw_info.buffer_unshare_reserve_bit);
  637. }
  638. }
  639. msleep(100);
  640. wait_time += 100;
  641. }
  642. for (epidx = 0; epidx < hw->max_epid; epidx++) {
  643. if (epidx == hw->my_epid)
  644. continue;
  645. if (test_bit(epidx, &hw->hw_info.buffer_unshare_reserve_bit))
  646. clear_bit(epidx,
  647. &hw->hw_info.buffer_unshare_reserve_bit);
  648. }
  649. return (wait_time < FJES_COMMAND_EPSTOP_WAIT_TIMEOUT * 1000)
  650. ? 0 : -EBUSY;
  651. }
  652. bool fjes_hw_check_epbuf_version(struct epbuf_handler *epbh, u32 version)
  653. {
  654. union ep_buffer_info *info = epbh->info;
  655. return (info->common.version == version);
  656. }
  657. bool fjes_hw_check_mtu(struct epbuf_handler *epbh, u32 mtu)
  658. {
  659. union ep_buffer_info *info = epbh->info;
  660. return ((info->v1i.frame_max == FJES_MTU_TO_FRAME_SIZE(mtu)) &&
  661. info->v1i.rx_status & FJES_RX_MTU_CHANGING_DONE);
  662. }
  663. bool fjes_hw_check_vlan_id(struct epbuf_handler *epbh, u16 vlan_id)
  664. {
  665. union ep_buffer_info *info = epbh->info;
  666. bool ret = false;
  667. int i;
  668. if (vlan_id == 0) {
  669. ret = true;
  670. } else {
  671. for (i = 0; i < EP_BUFFER_SUPPORT_VLAN_MAX; i++) {
  672. if (vlan_id == info->v1i.vlan_id[i]) {
  673. ret = true;
  674. break;
  675. }
  676. }
  677. }
  678. return ret;
  679. }
  680. bool fjes_hw_set_vlan_id(struct epbuf_handler *epbh, u16 vlan_id)
  681. {
  682. union ep_buffer_info *info = epbh->info;
  683. int i;
  684. for (i = 0; i < EP_BUFFER_SUPPORT_VLAN_MAX; i++) {
  685. if (info->v1i.vlan_id[i] == 0) {
  686. info->v1i.vlan_id[i] = vlan_id;
  687. return true;
  688. }
  689. }
  690. return false;
  691. }
  692. void fjes_hw_del_vlan_id(struct epbuf_handler *epbh, u16 vlan_id)
  693. {
  694. union ep_buffer_info *info = epbh->info;
  695. int i;
  696. if (0 != vlan_id) {
  697. for (i = 0; i < EP_BUFFER_SUPPORT_VLAN_MAX; i++) {
  698. if (vlan_id == info->v1i.vlan_id[i])
  699. info->v1i.vlan_id[i] = 0;
  700. }
  701. }
  702. }
  703. bool fjes_hw_epbuf_rx_is_empty(struct epbuf_handler *epbh)
  704. {
  705. union ep_buffer_info *info = epbh->info;
  706. if (!(info->v1i.rx_status & FJES_RX_MTU_CHANGING_DONE))
  707. return true;
  708. if (info->v1i.count_max == 0)
  709. return true;
  710. return EP_RING_EMPTY(info->v1i.head, info->v1i.tail,
  711. info->v1i.count_max);
  712. }
  713. void *fjes_hw_epbuf_rx_curpkt_get_addr(struct epbuf_handler *epbh,
  714. size_t *psize)
  715. {
  716. union ep_buffer_info *info = epbh->info;
  717. struct esmem_frame *ring_frame;
  718. void *frame;
  719. ring_frame = (struct esmem_frame *)&(epbh->ring[EP_RING_INDEX
  720. (info->v1i.head,
  721. info->v1i.count_max) *
  722. info->v1i.frame_max]);
  723. *psize = (size_t)ring_frame->frame_size;
  724. frame = ring_frame->frame_data;
  725. return frame;
  726. }
  727. void fjes_hw_epbuf_rx_curpkt_drop(struct epbuf_handler *epbh)
  728. {
  729. union ep_buffer_info *info = epbh->info;
  730. if (fjes_hw_epbuf_rx_is_empty(epbh))
  731. return;
  732. EP_RING_INDEX_INC(epbh->info->v1i.head, info->v1i.count_max);
  733. }
  734. int fjes_hw_epbuf_tx_pkt_send(struct epbuf_handler *epbh,
  735. void *frame, size_t size)
  736. {
  737. union ep_buffer_info *info = epbh->info;
  738. struct esmem_frame *ring_frame;
  739. if (EP_RING_FULL(info->v1i.head, info->v1i.tail, info->v1i.count_max))
  740. return -ENOBUFS;
  741. ring_frame = (struct esmem_frame *)&(epbh->ring[EP_RING_INDEX
  742. (info->v1i.tail - 1,
  743. info->v1i.count_max) *
  744. info->v1i.frame_max]);
  745. ring_frame->frame_size = size;
  746. memcpy((void *)(ring_frame->frame_data), (void *)frame, size);
  747. EP_RING_INDEX_INC(epbh->info->v1i.tail, info->v1i.count_max);
  748. return 0;
  749. }
  750. static void fjes_hw_update_zone_task(struct work_struct *work)
  751. {
  752. struct fjes_hw *hw = container_of(work,
  753. struct fjes_hw, update_zone_task);
  754. struct my_s {u8 es_status; u8 zone; } *info;
  755. union fjes_device_command_res *res_buf;
  756. enum ep_partner_status pstatus;
  757. struct fjes_adapter *adapter;
  758. struct net_device *netdev;
  759. unsigned long flags;
  760. ulong unshare_bit = 0;
  761. ulong share_bit = 0;
  762. ulong irq_bit = 0;
  763. int epidx;
  764. int ret;
  765. adapter = (struct fjes_adapter *)hw->back;
  766. netdev = adapter->netdev;
  767. res_buf = hw->hw_info.res_buf;
  768. info = (struct my_s *)&res_buf->info.info;
  769. mutex_lock(&hw->hw_info.lock);
  770. ret = fjes_hw_request_info(hw);
  771. switch (ret) {
  772. case -ENOMSG:
  773. case -EBUSY:
  774. default:
  775. if (!work_pending(&adapter->force_close_task)) {
  776. adapter->force_reset = true;
  777. schedule_work(&adapter->force_close_task);
  778. }
  779. break;
  780. case 0:
  781. for (epidx = 0; epidx < hw->max_epid; epidx++) {
  782. if (epidx == hw->my_epid) {
  783. hw->ep_shm_info[epidx].es_status =
  784. info[epidx].es_status;
  785. hw->ep_shm_info[epidx].zone =
  786. info[epidx].zone;
  787. continue;
  788. }
  789. pstatus = fjes_hw_get_partner_ep_status(hw, epidx);
  790. switch (pstatus) {
  791. case EP_PARTNER_UNSHARE:
  792. default:
  793. if ((info[epidx].zone !=
  794. FJES_ZONING_ZONE_TYPE_NONE) &&
  795. (info[epidx].es_status ==
  796. FJES_ZONING_STATUS_ENABLE) &&
  797. (info[epidx].zone ==
  798. info[hw->my_epid].zone))
  799. set_bit(epidx, &share_bit);
  800. else
  801. set_bit(epidx, &unshare_bit);
  802. break;
  803. case EP_PARTNER_COMPLETE:
  804. case EP_PARTNER_WAITING:
  805. if ((info[epidx].zone ==
  806. FJES_ZONING_ZONE_TYPE_NONE) ||
  807. (info[epidx].es_status !=
  808. FJES_ZONING_STATUS_ENABLE) ||
  809. (info[epidx].zone !=
  810. info[hw->my_epid].zone)) {
  811. set_bit(epidx,
  812. &adapter->unshare_watch_bitmask);
  813. set_bit(epidx,
  814. &hw->hw_info.buffer_unshare_reserve_bit);
  815. }
  816. break;
  817. case EP_PARTNER_SHARED:
  818. if ((info[epidx].zone ==
  819. FJES_ZONING_ZONE_TYPE_NONE) ||
  820. (info[epidx].es_status !=
  821. FJES_ZONING_STATUS_ENABLE) ||
  822. (info[epidx].zone !=
  823. info[hw->my_epid].zone))
  824. set_bit(epidx, &irq_bit);
  825. break;
  826. }
  827. hw->ep_shm_info[epidx].es_status =
  828. info[epidx].es_status;
  829. hw->ep_shm_info[epidx].zone = info[epidx].zone;
  830. }
  831. break;
  832. }
  833. mutex_unlock(&hw->hw_info.lock);
  834. for (epidx = 0; epidx < hw->max_epid; epidx++) {
  835. if (epidx == hw->my_epid)
  836. continue;
  837. if (test_bit(epidx, &share_bit)) {
  838. spin_lock_irqsave(&hw->rx_status_lock, flags);
  839. fjes_hw_setup_epbuf(&hw->ep_shm_info[epidx].tx,
  840. netdev->dev_addr, netdev->mtu);
  841. spin_unlock_irqrestore(&hw->rx_status_lock, flags);
  842. mutex_lock(&hw->hw_info.lock);
  843. ret = fjes_hw_register_buff_addr(
  844. hw, epidx, &hw->ep_shm_info[epidx]);
  845. switch (ret) {
  846. case 0:
  847. break;
  848. case -ENOMSG:
  849. case -EBUSY:
  850. default:
  851. if (!work_pending(&adapter->force_close_task)) {
  852. adapter->force_reset = true;
  853. schedule_work(
  854. &adapter->force_close_task);
  855. }
  856. break;
  857. }
  858. mutex_unlock(&hw->hw_info.lock);
  859. }
  860. if (test_bit(epidx, &unshare_bit)) {
  861. mutex_lock(&hw->hw_info.lock);
  862. ret = fjes_hw_unregister_buff_addr(hw, epidx);
  863. switch (ret) {
  864. case 0:
  865. break;
  866. case -ENOMSG:
  867. case -EBUSY:
  868. default:
  869. if (!work_pending(&adapter->force_close_task)) {
  870. adapter->force_reset = true;
  871. schedule_work(
  872. &adapter->force_close_task);
  873. }
  874. break;
  875. }
  876. mutex_unlock(&hw->hw_info.lock);
  877. if (ret == 0) {
  878. spin_lock_irqsave(&hw->rx_status_lock, flags);
  879. fjes_hw_setup_epbuf(
  880. &hw->ep_shm_info[epidx].tx,
  881. netdev->dev_addr, netdev->mtu);
  882. spin_unlock_irqrestore(&hw->rx_status_lock,
  883. flags);
  884. }
  885. }
  886. if (test_bit(epidx, &irq_bit)) {
  887. fjes_hw_raise_interrupt(hw, epidx,
  888. REG_ICTL_MASK_TXRX_STOP_REQ);
  889. set_bit(epidx, &hw->txrx_stop_req_bit);
  890. spin_lock_irqsave(&hw->rx_status_lock, flags);
  891. hw->ep_shm_info[epidx].tx.
  892. info->v1i.rx_status |=
  893. FJES_RX_STOP_REQ_REQUEST;
  894. spin_unlock_irqrestore(&hw->rx_status_lock, flags);
  895. set_bit(epidx, &hw->hw_info.buffer_unshare_reserve_bit);
  896. }
  897. }
  898. if (irq_bit || adapter->unshare_watch_bitmask) {
  899. if (!work_pending(&adapter->unshare_watch_task))
  900. queue_work(adapter->control_wq,
  901. &adapter->unshare_watch_task);
  902. }
  903. }
  904. static void fjes_hw_epstop_task(struct work_struct *work)
  905. {
  906. struct fjes_hw *hw = container_of(work, struct fjes_hw, epstop_task);
  907. struct fjes_adapter *adapter = (struct fjes_adapter *)hw->back;
  908. unsigned long flags;
  909. ulong remain_bit;
  910. int epid_bit;
  911. while ((remain_bit = hw->epstop_req_bit)) {
  912. for (epid_bit = 0; remain_bit; remain_bit >>= 1, epid_bit++) {
  913. if (remain_bit & 1) {
  914. spin_lock_irqsave(&hw->rx_status_lock, flags);
  915. hw->ep_shm_info[epid_bit].
  916. tx.info->v1i.rx_status |=
  917. FJES_RX_STOP_REQ_DONE;
  918. spin_unlock_irqrestore(&hw->rx_status_lock,
  919. flags);
  920. clear_bit(epid_bit, &hw->epstop_req_bit);
  921. set_bit(epid_bit,
  922. &adapter->unshare_watch_bitmask);
  923. if (!work_pending(&adapter->unshare_watch_task))
  924. queue_work(
  925. adapter->control_wq,
  926. &adapter->unshare_watch_task);
  927. }
  928. }
  929. }
  930. }