rx.c 28 KB

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  1. /****************************************************************************
  2. * Driver for Solarflare network controllers and boards
  3. * Copyright 2005-2006 Fen Systems Ltd.
  4. * Copyright 2005-2013 Solarflare Communications Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License version 2 as published
  8. * by the Free Software Foundation, incorporated herein by reference.
  9. */
  10. #include <linux/socket.h>
  11. #include <linux/in.h>
  12. #include <linux/slab.h>
  13. #include <linux/ip.h>
  14. #include <linux/ipv6.h>
  15. #include <linux/tcp.h>
  16. #include <linux/udp.h>
  17. #include <linux/prefetch.h>
  18. #include <linux/moduleparam.h>
  19. #include <linux/iommu.h>
  20. #include <net/ip.h>
  21. #include <net/checksum.h>
  22. #include "net_driver.h"
  23. #include "efx.h"
  24. #include "filter.h"
  25. #include "nic.h"
  26. #include "selftest.h"
  27. #include "workarounds.h"
  28. /* Preferred number of descriptors to fill at once */
  29. #define EFX_RX_PREFERRED_BATCH 8U
  30. /* Number of RX buffers to recycle pages for. When creating the RX page recycle
  31. * ring, this number is divided by the number of buffers per page to calculate
  32. * the number of pages to store in the RX page recycle ring.
  33. */
  34. #define EFX_RECYCLE_RING_SIZE_IOMMU 4096
  35. #define EFX_RECYCLE_RING_SIZE_NOIOMMU (2 * EFX_RX_PREFERRED_BATCH)
  36. /* Size of buffer allocated for skb header area. */
  37. #define EFX_SKB_HEADERS 128u
  38. /* This is the percentage fill level below which new RX descriptors
  39. * will be added to the RX descriptor ring.
  40. */
  41. static unsigned int rx_refill_threshold;
  42. /* Each packet can consume up to ceil(max_frame_len / buffer_size) buffers */
  43. #define EFX_RX_MAX_FRAGS DIV_ROUND_UP(EFX_MAX_FRAME_LEN(EFX_MAX_MTU), \
  44. EFX_RX_USR_BUF_SIZE)
  45. /*
  46. * RX maximum head room required.
  47. *
  48. * This must be at least 1 to prevent overflow, plus one packet-worth
  49. * to allow pipelined receives.
  50. */
  51. #define EFX_RXD_HEAD_ROOM (1 + EFX_RX_MAX_FRAGS)
  52. static inline u8 *efx_rx_buf_va(struct efx_rx_buffer *buf)
  53. {
  54. return page_address(buf->page) + buf->page_offset;
  55. }
  56. static inline u32 efx_rx_buf_hash(struct efx_nic *efx, const u8 *eh)
  57. {
  58. #if defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
  59. return __le32_to_cpup((const __le32 *)(eh + efx->rx_packet_hash_offset));
  60. #else
  61. const u8 *data = eh + efx->rx_packet_hash_offset;
  62. return (u32)data[0] |
  63. (u32)data[1] << 8 |
  64. (u32)data[2] << 16 |
  65. (u32)data[3] << 24;
  66. #endif
  67. }
  68. static inline struct efx_rx_buffer *
  69. efx_rx_buf_next(struct efx_rx_queue *rx_queue, struct efx_rx_buffer *rx_buf)
  70. {
  71. if (unlikely(rx_buf == efx_rx_buffer(rx_queue, rx_queue->ptr_mask)))
  72. return efx_rx_buffer(rx_queue, 0);
  73. else
  74. return rx_buf + 1;
  75. }
  76. static inline void efx_sync_rx_buffer(struct efx_nic *efx,
  77. struct efx_rx_buffer *rx_buf,
  78. unsigned int len)
  79. {
  80. dma_sync_single_for_cpu(&efx->pci_dev->dev, rx_buf->dma_addr, len,
  81. DMA_FROM_DEVICE);
  82. }
  83. void efx_rx_config_page_split(struct efx_nic *efx)
  84. {
  85. efx->rx_page_buf_step = ALIGN(efx->rx_dma_len + efx->rx_ip_align,
  86. EFX_RX_BUF_ALIGNMENT);
  87. efx->rx_bufs_per_page = efx->rx_buffer_order ? 1 :
  88. ((PAGE_SIZE - sizeof(struct efx_rx_page_state)) /
  89. efx->rx_page_buf_step);
  90. efx->rx_buffer_truesize = (PAGE_SIZE << efx->rx_buffer_order) /
  91. efx->rx_bufs_per_page;
  92. efx->rx_pages_per_batch = DIV_ROUND_UP(EFX_RX_PREFERRED_BATCH,
  93. efx->rx_bufs_per_page);
  94. }
  95. /* Check the RX page recycle ring for a page that can be reused. */
  96. static struct page *efx_reuse_page(struct efx_rx_queue *rx_queue)
  97. {
  98. struct efx_nic *efx = rx_queue->efx;
  99. struct page *page;
  100. struct efx_rx_page_state *state;
  101. unsigned index;
  102. index = rx_queue->page_remove & rx_queue->page_ptr_mask;
  103. page = rx_queue->page_ring[index];
  104. if (page == NULL)
  105. return NULL;
  106. rx_queue->page_ring[index] = NULL;
  107. /* page_remove cannot exceed page_add. */
  108. if (rx_queue->page_remove != rx_queue->page_add)
  109. ++rx_queue->page_remove;
  110. /* If page_count is 1 then we hold the only reference to this page. */
  111. if (page_count(page) == 1) {
  112. ++rx_queue->page_recycle_count;
  113. return page;
  114. } else {
  115. state = page_address(page);
  116. dma_unmap_page(&efx->pci_dev->dev, state->dma_addr,
  117. PAGE_SIZE << efx->rx_buffer_order,
  118. DMA_FROM_DEVICE);
  119. put_page(page);
  120. ++rx_queue->page_recycle_failed;
  121. }
  122. return NULL;
  123. }
  124. /**
  125. * efx_init_rx_buffers - create EFX_RX_BATCH page-based RX buffers
  126. *
  127. * @rx_queue: Efx RX queue
  128. *
  129. * This allocates a batch of pages, maps them for DMA, and populates
  130. * struct efx_rx_buffers for each one. Return a negative error code or
  131. * 0 on success. If a single page can be used for multiple buffers,
  132. * then the page will either be inserted fully, or not at all.
  133. */
  134. static int efx_init_rx_buffers(struct efx_rx_queue *rx_queue, bool atomic)
  135. {
  136. struct efx_nic *efx = rx_queue->efx;
  137. struct efx_rx_buffer *rx_buf;
  138. struct page *page;
  139. unsigned int page_offset;
  140. struct efx_rx_page_state *state;
  141. dma_addr_t dma_addr;
  142. unsigned index, count;
  143. count = 0;
  144. do {
  145. page = efx_reuse_page(rx_queue);
  146. if (page == NULL) {
  147. page = alloc_pages(__GFP_COLD | __GFP_COMP |
  148. (atomic ? GFP_ATOMIC : GFP_KERNEL),
  149. efx->rx_buffer_order);
  150. if (unlikely(page == NULL))
  151. return -ENOMEM;
  152. dma_addr =
  153. dma_map_page(&efx->pci_dev->dev, page, 0,
  154. PAGE_SIZE << efx->rx_buffer_order,
  155. DMA_FROM_DEVICE);
  156. if (unlikely(dma_mapping_error(&efx->pci_dev->dev,
  157. dma_addr))) {
  158. __free_pages(page, efx->rx_buffer_order);
  159. return -EIO;
  160. }
  161. state = page_address(page);
  162. state->dma_addr = dma_addr;
  163. } else {
  164. state = page_address(page);
  165. dma_addr = state->dma_addr;
  166. }
  167. dma_addr += sizeof(struct efx_rx_page_state);
  168. page_offset = sizeof(struct efx_rx_page_state);
  169. do {
  170. index = rx_queue->added_count & rx_queue->ptr_mask;
  171. rx_buf = efx_rx_buffer(rx_queue, index);
  172. rx_buf->dma_addr = dma_addr + efx->rx_ip_align;
  173. rx_buf->page = page;
  174. rx_buf->page_offset = page_offset + efx->rx_ip_align;
  175. rx_buf->len = efx->rx_dma_len;
  176. rx_buf->flags = 0;
  177. ++rx_queue->added_count;
  178. get_page(page);
  179. dma_addr += efx->rx_page_buf_step;
  180. page_offset += efx->rx_page_buf_step;
  181. } while (page_offset + efx->rx_page_buf_step <= PAGE_SIZE);
  182. rx_buf->flags = EFX_RX_BUF_LAST_IN_PAGE;
  183. } while (++count < efx->rx_pages_per_batch);
  184. return 0;
  185. }
  186. /* Unmap a DMA-mapped page. This function is only called for the final RX
  187. * buffer in a page.
  188. */
  189. static void efx_unmap_rx_buffer(struct efx_nic *efx,
  190. struct efx_rx_buffer *rx_buf)
  191. {
  192. struct page *page = rx_buf->page;
  193. if (page) {
  194. struct efx_rx_page_state *state = page_address(page);
  195. dma_unmap_page(&efx->pci_dev->dev,
  196. state->dma_addr,
  197. PAGE_SIZE << efx->rx_buffer_order,
  198. DMA_FROM_DEVICE);
  199. }
  200. }
  201. static void efx_free_rx_buffers(struct efx_rx_queue *rx_queue,
  202. struct efx_rx_buffer *rx_buf,
  203. unsigned int num_bufs)
  204. {
  205. do {
  206. if (rx_buf->page) {
  207. put_page(rx_buf->page);
  208. rx_buf->page = NULL;
  209. }
  210. rx_buf = efx_rx_buf_next(rx_queue, rx_buf);
  211. } while (--num_bufs);
  212. }
  213. /* Attempt to recycle the page if there is an RX recycle ring; the page can
  214. * only be added if this is the final RX buffer, to prevent pages being used in
  215. * the descriptor ring and appearing in the recycle ring simultaneously.
  216. */
  217. static void efx_recycle_rx_page(struct efx_channel *channel,
  218. struct efx_rx_buffer *rx_buf)
  219. {
  220. struct page *page = rx_buf->page;
  221. struct efx_rx_queue *rx_queue = efx_channel_get_rx_queue(channel);
  222. struct efx_nic *efx = rx_queue->efx;
  223. unsigned index;
  224. /* Only recycle the page after processing the final buffer. */
  225. if (!(rx_buf->flags & EFX_RX_BUF_LAST_IN_PAGE))
  226. return;
  227. index = rx_queue->page_add & rx_queue->page_ptr_mask;
  228. if (rx_queue->page_ring[index] == NULL) {
  229. unsigned read_index = rx_queue->page_remove &
  230. rx_queue->page_ptr_mask;
  231. /* The next slot in the recycle ring is available, but
  232. * increment page_remove if the read pointer currently
  233. * points here.
  234. */
  235. if (read_index == index)
  236. ++rx_queue->page_remove;
  237. rx_queue->page_ring[index] = page;
  238. ++rx_queue->page_add;
  239. return;
  240. }
  241. ++rx_queue->page_recycle_full;
  242. efx_unmap_rx_buffer(efx, rx_buf);
  243. put_page(rx_buf->page);
  244. }
  245. static void efx_fini_rx_buffer(struct efx_rx_queue *rx_queue,
  246. struct efx_rx_buffer *rx_buf)
  247. {
  248. /* Release the page reference we hold for the buffer. */
  249. if (rx_buf->page)
  250. put_page(rx_buf->page);
  251. /* If this is the last buffer in a page, unmap and free it. */
  252. if (rx_buf->flags & EFX_RX_BUF_LAST_IN_PAGE) {
  253. efx_unmap_rx_buffer(rx_queue->efx, rx_buf);
  254. efx_free_rx_buffers(rx_queue, rx_buf, 1);
  255. }
  256. rx_buf->page = NULL;
  257. }
  258. /* Recycle the pages that are used by buffers that have just been received. */
  259. static void efx_recycle_rx_pages(struct efx_channel *channel,
  260. struct efx_rx_buffer *rx_buf,
  261. unsigned int n_frags)
  262. {
  263. struct efx_rx_queue *rx_queue = efx_channel_get_rx_queue(channel);
  264. do {
  265. efx_recycle_rx_page(channel, rx_buf);
  266. rx_buf = efx_rx_buf_next(rx_queue, rx_buf);
  267. } while (--n_frags);
  268. }
  269. static void efx_discard_rx_packet(struct efx_channel *channel,
  270. struct efx_rx_buffer *rx_buf,
  271. unsigned int n_frags)
  272. {
  273. struct efx_rx_queue *rx_queue = efx_channel_get_rx_queue(channel);
  274. efx_recycle_rx_pages(channel, rx_buf, n_frags);
  275. efx_free_rx_buffers(rx_queue, rx_buf, n_frags);
  276. }
  277. /**
  278. * efx_fast_push_rx_descriptors - push new RX descriptors quickly
  279. * @rx_queue: RX descriptor queue
  280. *
  281. * This will aim to fill the RX descriptor queue up to
  282. * @rx_queue->@max_fill. If there is insufficient atomic
  283. * memory to do so, a slow fill will be scheduled.
  284. *
  285. * The caller must provide serialisation (none is used here). In practise,
  286. * this means this function must run from the NAPI handler, or be called
  287. * when NAPI is disabled.
  288. */
  289. void efx_fast_push_rx_descriptors(struct efx_rx_queue *rx_queue, bool atomic)
  290. {
  291. struct efx_nic *efx = rx_queue->efx;
  292. unsigned int fill_level, batch_size;
  293. int space, rc = 0;
  294. if (!rx_queue->refill_enabled)
  295. return;
  296. /* Calculate current fill level, and exit if we don't need to fill */
  297. fill_level = (rx_queue->added_count - rx_queue->removed_count);
  298. EFX_BUG_ON_PARANOID(fill_level > rx_queue->efx->rxq_entries);
  299. if (fill_level >= rx_queue->fast_fill_trigger)
  300. goto out;
  301. /* Record minimum fill level */
  302. if (unlikely(fill_level < rx_queue->min_fill)) {
  303. if (fill_level)
  304. rx_queue->min_fill = fill_level;
  305. }
  306. batch_size = efx->rx_pages_per_batch * efx->rx_bufs_per_page;
  307. space = rx_queue->max_fill - fill_level;
  308. EFX_BUG_ON_PARANOID(space < batch_size);
  309. netif_vdbg(rx_queue->efx, rx_status, rx_queue->efx->net_dev,
  310. "RX queue %d fast-filling descriptor ring from"
  311. " level %d to level %d\n",
  312. efx_rx_queue_index(rx_queue), fill_level,
  313. rx_queue->max_fill);
  314. do {
  315. rc = efx_init_rx_buffers(rx_queue, atomic);
  316. if (unlikely(rc)) {
  317. /* Ensure that we don't leave the rx queue empty */
  318. if (rx_queue->added_count == rx_queue->removed_count)
  319. efx_schedule_slow_fill(rx_queue);
  320. goto out;
  321. }
  322. } while ((space -= batch_size) >= batch_size);
  323. netif_vdbg(rx_queue->efx, rx_status, rx_queue->efx->net_dev,
  324. "RX queue %d fast-filled descriptor ring "
  325. "to level %d\n", efx_rx_queue_index(rx_queue),
  326. rx_queue->added_count - rx_queue->removed_count);
  327. out:
  328. if (rx_queue->notified_count != rx_queue->added_count)
  329. efx_nic_notify_rx_desc(rx_queue);
  330. }
  331. void efx_rx_slow_fill(unsigned long context)
  332. {
  333. struct efx_rx_queue *rx_queue = (struct efx_rx_queue *)context;
  334. /* Post an event to cause NAPI to run and refill the queue */
  335. efx_nic_generate_fill_event(rx_queue);
  336. ++rx_queue->slow_fill_count;
  337. }
  338. static void efx_rx_packet__check_len(struct efx_rx_queue *rx_queue,
  339. struct efx_rx_buffer *rx_buf,
  340. int len)
  341. {
  342. struct efx_nic *efx = rx_queue->efx;
  343. unsigned max_len = rx_buf->len - efx->type->rx_buffer_padding;
  344. if (likely(len <= max_len))
  345. return;
  346. /* The packet must be discarded, but this is only a fatal error
  347. * if the caller indicated it was
  348. */
  349. rx_buf->flags |= EFX_RX_PKT_DISCARD;
  350. if ((len > rx_buf->len) && EFX_WORKAROUND_8071(efx)) {
  351. if (net_ratelimit())
  352. netif_err(efx, rx_err, efx->net_dev,
  353. " RX queue %d seriously overlength "
  354. "RX event (0x%x > 0x%x+0x%x). Leaking\n",
  355. efx_rx_queue_index(rx_queue), len, max_len,
  356. efx->type->rx_buffer_padding);
  357. efx_schedule_reset(efx, RESET_TYPE_RX_RECOVERY);
  358. } else {
  359. if (net_ratelimit())
  360. netif_err(efx, rx_err, efx->net_dev,
  361. " RX queue %d overlength RX event "
  362. "(0x%x > 0x%x)\n",
  363. efx_rx_queue_index(rx_queue), len, max_len);
  364. }
  365. efx_rx_queue_channel(rx_queue)->n_rx_overlength++;
  366. }
  367. /* Pass a received packet up through GRO. GRO can handle pages
  368. * regardless of checksum state and skbs with a good checksum.
  369. */
  370. static void
  371. efx_rx_packet_gro(struct efx_channel *channel, struct efx_rx_buffer *rx_buf,
  372. unsigned int n_frags, u8 *eh)
  373. {
  374. struct napi_struct *napi = &channel->napi_str;
  375. gro_result_t gro_result;
  376. struct efx_nic *efx = channel->efx;
  377. struct sk_buff *skb;
  378. skb = napi_get_frags(napi);
  379. if (unlikely(!skb)) {
  380. struct efx_rx_queue *rx_queue;
  381. rx_queue = efx_channel_get_rx_queue(channel);
  382. efx_free_rx_buffers(rx_queue, rx_buf, n_frags);
  383. return;
  384. }
  385. if (efx->net_dev->features & NETIF_F_RXHASH)
  386. skb_set_hash(skb, efx_rx_buf_hash(efx, eh),
  387. PKT_HASH_TYPE_L3);
  388. skb->ip_summed = ((rx_buf->flags & EFX_RX_PKT_CSUMMED) ?
  389. CHECKSUM_UNNECESSARY : CHECKSUM_NONE);
  390. for (;;) {
  391. skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
  392. rx_buf->page, rx_buf->page_offset,
  393. rx_buf->len);
  394. rx_buf->page = NULL;
  395. skb->len += rx_buf->len;
  396. if (skb_shinfo(skb)->nr_frags == n_frags)
  397. break;
  398. rx_buf = efx_rx_buf_next(&channel->rx_queue, rx_buf);
  399. }
  400. skb->data_len = skb->len;
  401. skb->truesize += n_frags * efx->rx_buffer_truesize;
  402. skb_record_rx_queue(skb, channel->rx_queue.core_index);
  403. gro_result = napi_gro_frags(napi);
  404. if (gro_result != GRO_DROP)
  405. channel->irq_mod_score += 2;
  406. }
  407. /* Allocate and construct an SKB around page fragments */
  408. static struct sk_buff *efx_rx_mk_skb(struct efx_channel *channel,
  409. struct efx_rx_buffer *rx_buf,
  410. unsigned int n_frags,
  411. u8 *eh, int hdr_len)
  412. {
  413. struct efx_nic *efx = channel->efx;
  414. struct sk_buff *skb;
  415. /* Allocate an SKB to store the headers */
  416. skb = netdev_alloc_skb(efx->net_dev,
  417. efx->rx_ip_align + efx->rx_prefix_size +
  418. hdr_len);
  419. if (unlikely(skb == NULL)) {
  420. atomic_inc(&efx->n_rx_noskb_drops);
  421. return NULL;
  422. }
  423. EFX_BUG_ON_PARANOID(rx_buf->len < hdr_len);
  424. memcpy(skb->data + efx->rx_ip_align, eh - efx->rx_prefix_size,
  425. efx->rx_prefix_size + hdr_len);
  426. skb_reserve(skb, efx->rx_ip_align + efx->rx_prefix_size);
  427. __skb_put(skb, hdr_len);
  428. /* Append the remaining page(s) onto the frag list */
  429. if (rx_buf->len > hdr_len) {
  430. rx_buf->page_offset += hdr_len;
  431. rx_buf->len -= hdr_len;
  432. for (;;) {
  433. skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
  434. rx_buf->page, rx_buf->page_offset,
  435. rx_buf->len);
  436. rx_buf->page = NULL;
  437. skb->len += rx_buf->len;
  438. skb->data_len += rx_buf->len;
  439. if (skb_shinfo(skb)->nr_frags == n_frags)
  440. break;
  441. rx_buf = efx_rx_buf_next(&channel->rx_queue, rx_buf);
  442. }
  443. } else {
  444. __free_pages(rx_buf->page, efx->rx_buffer_order);
  445. rx_buf->page = NULL;
  446. n_frags = 0;
  447. }
  448. skb->truesize += n_frags * efx->rx_buffer_truesize;
  449. /* Move past the ethernet header */
  450. skb->protocol = eth_type_trans(skb, efx->net_dev);
  451. skb_mark_napi_id(skb, &channel->napi_str);
  452. return skb;
  453. }
  454. void efx_rx_packet(struct efx_rx_queue *rx_queue, unsigned int index,
  455. unsigned int n_frags, unsigned int len, u16 flags)
  456. {
  457. struct efx_nic *efx = rx_queue->efx;
  458. struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
  459. struct efx_rx_buffer *rx_buf;
  460. rx_queue->rx_packets++;
  461. rx_buf = efx_rx_buffer(rx_queue, index);
  462. rx_buf->flags |= flags;
  463. /* Validate the number of fragments and completed length */
  464. if (n_frags == 1) {
  465. if (!(flags & EFX_RX_PKT_PREFIX_LEN))
  466. efx_rx_packet__check_len(rx_queue, rx_buf, len);
  467. } else if (unlikely(n_frags > EFX_RX_MAX_FRAGS) ||
  468. unlikely(len <= (n_frags - 1) * efx->rx_dma_len) ||
  469. unlikely(len > n_frags * efx->rx_dma_len) ||
  470. unlikely(!efx->rx_scatter)) {
  471. /* If this isn't an explicit discard request, either
  472. * the hardware or the driver is broken.
  473. */
  474. WARN_ON(!(len == 0 && rx_buf->flags & EFX_RX_PKT_DISCARD));
  475. rx_buf->flags |= EFX_RX_PKT_DISCARD;
  476. }
  477. netif_vdbg(efx, rx_status, efx->net_dev,
  478. "RX queue %d received ids %x-%x len %d %s%s\n",
  479. efx_rx_queue_index(rx_queue), index,
  480. (index + n_frags - 1) & rx_queue->ptr_mask, len,
  481. (rx_buf->flags & EFX_RX_PKT_CSUMMED) ? " [SUMMED]" : "",
  482. (rx_buf->flags & EFX_RX_PKT_DISCARD) ? " [DISCARD]" : "");
  483. /* Discard packet, if instructed to do so. Process the
  484. * previous receive first.
  485. */
  486. if (unlikely(rx_buf->flags & EFX_RX_PKT_DISCARD)) {
  487. efx_rx_flush_packet(channel);
  488. efx_discard_rx_packet(channel, rx_buf, n_frags);
  489. return;
  490. }
  491. if (n_frags == 1 && !(flags & EFX_RX_PKT_PREFIX_LEN))
  492. rx_buf->len = len;
  493. /* Release and/or sync the DMA mapping - assumes all RX buffers
  494. * consumed in-order per RX queue.
  495. */
  496. efx_sync_rx_buffer(efx, rx_buf, rx_buf->len);
  497. /* Prefetch nice and early so data will (hopefully) be in cache by
  498. * the time we look at it.
  499. */
  500. prefetch(efx_rx_buf_va(rx_buf));
  501. rx_buf->page_offset += efx->rx_prefix_size;
  502. rx_buf->len -= efx->rx_prefix_size;
  503. if (n_frags > 1) {
  504. /* Release/sync DMA mapping for additional fragments.
  505. * Fix length for last fragment.
  506. */
  507. unsigned int tail_frags = n_frags - 1;
  508. for (;;) {
  509. rx_buf = efx_rx_buf_next(rx_queue, rx_buf);
  510. if (--tail_frags == 0)
  511. break;
  512. efx_sync_rx_buffer(efx, rx_buf, efx->rx_dma_len);
  513. }
  514. rx_buf->len = len - (n_frags - 1) * efx->rx_dma_len;
  515. efx_sync_rx_buffer(efx, rx_buf, rx_buf->len);
  516. }
  517. /* All fragments have been DMA-synced, so recycle pages. */
  518. rx_buf = efx_rx_buffer(rx_queue, index);
  519. efx_recycle_rx_pages(channel, rx_buf, n_frags);
  520. /* Pipeline receives so that we give time for packet headers to be
  521. * prefetched into cache.
  522. */
  523. efx_rx_flush_packet(channel);
  524. channel->rx_pkt_n_frags = n_frags;
  525. channel->rx_pkt_index = index;
  526. }
  527. static void efx_rx_deliver(struct efx_channel *channel, u8 *eh,
  528. struct efx_rx_buffer *rx_buf,
  529. unsigned int n_frags)
  530. {
  531. struct sk_buff *skb;
  532. u16 hdr_len = min_t(u16, rx_buf->len, EFX_SKB_HEADERS);
  533. skb = efx_rx_mk_skb(channel, rx_buf, n_frags, eh, hdr_len);
  534. if (unlikely(skb == NULL)) {
  535. struct efx_rx_queue *rx_queue;
  536. rx_queue = efx_channel_get_rx_queue(channel);
  537. efx_free_rx_buffers(rx_queue, rx_buf, n_frags);
  538. return;
  539. }
  540. skb_record_rx_queue(skb, channel->rx_queue.core_index);
  541. /* Set the SKB flags */
  542. skb_checksum_none_assert(skb);
  543. if (likely(rx_buf->flags & EFX_RX_PKT_CSUMMED))
  544. skb->ip_summed = CHECKSUM_UNNECESSARY;
  545. efx_rx_skb_attach_timestamp(channel, skb);
  546. if (channel->type->receive_skb)
  547. if (channel->type->receive_skb(channel, skb))
  548. return;
  549. /* Pass the packet up */
  550. netif_receive_skb(skb);
  551. }
  552. /* Handle a received packet. Second half: Touches packet payload. */
  553. void __efx_rx_packet(struct efx_channel *channel)
  554. {
  555. struct efx_nic *efx = channel->efx;
  556. struct efx_rx_buffer *rx_buf =
  557. efx_rx_buffer(&channel->rx_queue, channel->rx_pkt_index);
  558. u8 *eh = efx_rx_buf_va(rx_buf);
  559. /* Read length from the prefix if necessary. This already
  560. * excludes the length of the prefix itself.
  561. */
  562. if (rx_buf->flags & EFX_RX_PKT_PREFIX_LEN)
  563. rx_buf->len = le16_to_cpup((__le16 *)
  564. (eh + efx->rx_packet_len_offset));
  565. /* If we're in loopback test, then pass the packet directly to the
  566. * loopback layer, and free the rx_buf here
  567. */
  568. if (unlikely(efx->loopback_selftest)) {
  569. struct efx_rx_queue *rx_queue;
  570. efx_loopback_rx_packet(efx, eh, rx_buf->len);
  571. rx_queue = efx_channel_get_rx_queue(channel);
  572. efx_free_rx_buffers(rx_queue, rx_buf,
  573. channel->rx_pkt_n_frags);
  574. goto out;
  575. }
  576. if (unlikely(!(efx->net_dev->features & NETIF_F_RXCSUM)))
  577. rx_buf->flags &= ~EFX_RX_PKT_CSUMMED;
  578. if ((rx_buf->flags & EFX_RX_PKT_TCP) && !channel->type->receive_skb &&
  579. !efx_channel_busy_polling(channel))
  580. efx_rx_packet_gro(channel, rx_buf, channel->rx_pkt_n_frags, eh);
  581. else
  582. efx_rx_deliver(channel, eh, rx_buf, channel->rx_pkt_n_frags);
  583. out:
  584. channel->rx_pkt_n_frags = 0;
  585. }
  586. int efx_probe_rx_queue(struct efx_rx_queue *rx_queue)
  587. {
  588. struct efx_nic *efx = rx_queue->efx;
  589. unsigned int entries;
  590. int rc;
  591. /* Create the smallest power-of-two aligned ring */
  592. entries = max(roundup_pow_of_two(efx->rxq_entries), EFX_MIN_DMAQ_SIZE);
  593. EFX_BUG_ON_PARANOID(entries > EFX_MAX_DMAQ_SIZE);
  594. rx_queue->ptr_mask = entries - 1;
  595. netif_dbg(efx, probe, efx->net_dev,
  596. "creating RX queue %d size %#x mask %#x\n",
  597. efx_rx_queue_index(rx_queue), efx->rxq_entries,
  598. rx_queue->ptr_mask);
  599. /* Allocate RX buffers */
  600. rx_queue->buffer = kcalloc(entries, sizeof(*rx_queue->buffer),
  601. GFP_KERNEL);
  602. if (!rx_queue->buffer)
  603. return -ENOMEM;
  604. rc = efx_nic_probe_rx(rx_queue);
  605. if (rc) {
  606. kfree(rx_queue->buffer);
  607. rx_queue->buffer = NULL;
  608. }
  609. return rc;
  610. }
  611. static void efx_init_rx_recycle_ring(struct efx_nic *efx,
  612. struct efx_rx_queue *rx_queue)
  613. {
  614. unsigned int bufs_in_recycle_ring, page_ring_size;
  615. /* Set the RX recycle ring size */
  616. #ifdef CONFIG_PPC64
  617. bufs_in_recycle_ring = EFX_RECYCLE_RING_SIZE_IOMMU;
  618. #else
  619. if (iommu_present(&pci_bus_type))
  620. bufs_in_recycle_ring = EFX_RECYCLE_RING_SIZE_IOMMU;
  621. else
  622. bufs_in_recycle_ring = EFX_RECYCLE_RING_SIZE_NOIOMMU;
  623. #endif /* CONFIG_PPC64 */
  624. page_ring_size = roundup_pow_of_two(bufs_in_recycle_ring /
  625. efx->rx_bufs_per_page);
  626. rx_queue->page_ring = kcalloc(page_ring_size,
  627. sizeof(*rx_queue->page_ring), GFP_KERNEL);
  628. rx_queue->page_ptr_mask = page_ring_size - 1;
  629. }
  630. void efx_init_rx_queue(struct efx_rx_queue *rx_queue)
  631. {
  632. struct efx_nic *efx = rx_queue->efx;
  633. unsigned int max_fill, trigger, max_trigger;
  634. netif_dbg(rx_queue->efx, drv, rx_queue->efx->net_dev,
  635. "initialising RX queue %d\n", efx_rx_queue_index(rx_queue));
  636. /* Initialise ptr fields */
  637. rx_queue->added_count = 0;
  638. rx_queue->notified_count = 0;
  639. rx_queue->removed_count = 0;
  640. rx_queue->min_fill = -1U;
  641. efx_init_rx_recycle_ring(efx, rx_queue);
  642. rx_queue->page_remove = 0;
  643. rx_queue->page_add = rx_queue->page_ptr_mask + 1;
  644. rx_queue->page_recycle_count = 0;
  645. rx_queue->page_recycle_failed = 0;
  646. rx_queue->page_recycle_full = 0;
  647. /* Initialise limit fields */
  648. max_fill = efx->rxq_entries - EFX_RXD_HEAD_ROOM;
  649. max_trigger =
  650. max_fill - efx->rx_pages_per_batch * efx->rx_bufs_per_page;
  651. if (rx_refill_threshold != 0) {
  652. trigger = max_fill * min(rx_refill_threshold, 100U) / 100U;
  653. if (trigger > max_trigger)
  654. trigger = max_trigger;
  655. } else {
  656. trigger = max_trigger;
  657. }
  658. rx_queue->max_fill = max_fill;
  659. rx_queue->fast_fill_trigger = trigger;
  660. rx_queue->refill_enabled = true;
  661. /* Set up RX descriptor ring */
  662. efx_nic_init_rx(rx_queue);
  663. }
  664. void efx_fini_rx_queue(struct efx_rx_queue *rx_queue)
  665. {
  666. int i;
  667. struct efx_nic *efx = rx_queue->efx;
  668. struct efx_rx_buffer *rx_buf;
  669. netif_dbg(rx_queue->efx, drv, rx_queue->efx->net_dev,
  670. "shutting down RX queue %d\n", efx_rx_queue_index(rx_queue));
  671. del_timer_sync(&rx_queue->slow_fill);
  672. /* Release RX buffers from the current read ptr to the write ptr */
  673. if (rx_queue->buffer) {
  674. for (i = rx_queue->removed_count; i < rx_queue->added_count;
  675. i++) {
  676. unsigned index = i & rx_queue->ptr_mask;
  677. rx_buf = efx_rx_buffer(rx_queue, index);
  678. efx_fini_rx_buffer(rx_queue, rx_buf);
  679. }
  680. }
  681. /* Unmap and release the pages in the recycle ring. Remove the ring. */
  682. for (i = 0; i <= rx_queue->page_ptr_mask; i++) {
  683. struct page *page = rx_queue->page_ring[i];
  684. struct efx_rx_page_state *state;
  685. if (page == NULL)
  686. continue;
  687. state = page_address(page);
  688. dma_unmap_page(&efx->pci_dev->dev, state->dma_addr,
  689. PAGE_SIZE << efx->rx_buffer_order,
  690. DMA_FROM_DEVICE);
  691. put_page(page);
  692. }
  693. kfree(rx_queue->page_ring);
  694. rx_queue->page_ring = NULL;
  695. }
  696. void efx_remove_rx_queue(struct efx_rx_queue *rx_queue)
  697. {
  698. netif_dbg(rx_queue->efx, drv, rx_queue->efx->net_dev,
  699. "destroying RX queue %d\n", efx_rx_queue_index(rx_queue));
  700. efx_nic_remove_rx(rx_queue);
  701. kfree(rx_queue->buffer);
  702. rx_queue->buffer = NULL;
  703. }
  704. module_param(rx_refill_threshold, uint, 0444);
  705. MODULE_PARM_DESC(rx_refill_threshold,
  706. "RX descriptor ring refill threshold (%)");
  707. #ifdef CONFIG_RFS_ACCEL
  708. int efx_filter_rfs(struct net_device *net_dev, const struct sk_buff *skb,
  709. u16 rxq_index, u32 flow_id)
  710. {
  711. struct efx_nic *efx = netdev_priv(net_dev);
  712. struct efx_channel *channel;
  713. struct efx_filter_spec spec;
  714. struct flow_keys fk;
  715. int rc;
  716. if (flow_id == RPS_FLOW_ID_INVALID)
  717. return -EINVAL;
  718. if (!skb_flow_dissect_flow_keys(skb, &fk, 0))
  719. return -EPROTONOSUPPORT;
  720. if (fk.basic.n_proto != htons(ETH_P_IP) && fk.basic.n_proto != htons(ETH_P_IPV6))
  721. return -EPROTONOSUPPORT;
  722. if (fk.control.flags & FLOW_DIS_IS_FRAGMENT)
  723. return -EPROTONOSUPPORT;
  724. efx_filter_init_rx(&spec, EFX_FILTER_PRI_HINT,
  725. efx->rx_scatter ? EFX_FILTER_FLAG_RX_SCATTER : 0,
  726. rxq_index);
  727. spec.match_flags =
  728. EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_IP_PROTO |
  729. EFX_FILTER_MATCH_LOC_HOST | EFX_FILTER_MATCH_LOC_PORT |
  730. EFX_FILTER_MATCH_REM_HOST | EFX_FILTER_MATCH_REM_PORT;
  731. spec.ether_type = fk.basic.n_proto;
  732. spec.ip_proto = fk.basic.ip_proto;
  733. if (fk.basic.n_proto == htons(ETH_P_IP)) {
  734. spec.rem_host[0] = fk.addrs.v4addrs.src;
  735. spec.loc_host[0] = fk.addrs.v4addrs.dst;
  736. } else {
  737. memcpy(spec.rem_host, &fk.addrs.v6addrs.src, sizeof(struct in6_addr));
  738. memcpy(spec.loc_host, &fk.addrs.v6addrs.dst, sizeof(struct in6_addr));
  739. }
  740. spec.rem_port = fk.ports.src;
  741. spec.loc_port = fk.ports.dst;
  742. rc = efx->type->filter_rfs_insert(efx, &spec);
  743. if (rc < 0)
  744. return rc;
  745. /* Remember this so we can check whether to expire the filter later */
  746. channel = efx_get_channel(efx, rxq_index);
  747. channel->rps_flow_id[rc] = flow_id;
  748. ++channel->rfs_filters_added;
  749. if (spec.ether_type == htons(ETH_P_IP))
  750. netif_info(efx, rx_status, efx->net_dev,
  751. "steering %s %pI4:%u:%pI4:%u to queue %u [flow %u filter %d]\n",
  752. (spec.ip_proto == IPPROTO_TCP) ? "TCP" : "UDP",
  753. spec.rem_host, ntohs(spec.rem_port), spec.loc_host,
  754. ntohs(spec.loc_port), rxq_index, flow_id, rc);
  755. else
  756. netif_info(efx, rx_status, efx->net_dev,
  757. "steering %s [%pI6]:%u:[%pI6]:%u to queue %u [flow %u filter %d]\n",
  758. (spec.ip_proto == IPPROTO_TCP) ? "TCP" : "UDP",
  759. spec.rem_host, ntohs(spec.rem_port), spec.loc_host,
  760. ntohs(spec.loc_port), rxq_index, flow_id, rc);
  761. return rc;
  762. }
  763. bool __efx_filter_rfs_expire(struct efx_nic *efx, unsigned int quota)
  764. {
  765. bool (*expire_one)(struct efx_nic *efx, u32 flow_id, unsigned int index);
  766. unsigned int channel_idx, index, size;
  767. u32 flow_id;
  768. if (!spin_trylock_bh(&efx->filter_lock))
  769. return false;
  770. expire_one = efx->type->filter_rfs_expire_one;
  771. channel_idx = efx->rps_expire_channel;
  772. index = efx->rps_expire_index;
  773. size = efx->type->max_rx_ip_filters;
  774. while (quota--) {
  775. struct efx_channel *channel = efx_get_channel(efx, channel_idx);
  776. flow_id = channel->rps_flow_id[index];
  777. if (flow_id != RPS_FLOW_ID_INVALID &&
  778. expire_one(efx, flow_id, index)) {
  779. netif_info(efx, rx_status, efx->net_dev,
  780. "expired filter %d [queue %u flow %u]\n",
  781. index, channel_idx, flow_id);
  782. channel->rps_flow_id[index] = RPS_FLOW_ID_INVALID;
  783. }
  784. if (++index == size) {
  785. if (++channel_idx == efx->n_channels)
  786. channel_idx = 0;
  787. index = 0;
  788. }
  789. }
  790. efx->rps_expire_channel = channel_idx;
  791. efx->rps_expire_index = index;
  792. spin_unlock_bh(&efx->filter_lock);
  793. return true;
  794. }
  795. #endif /* CONFIG_RFS_ACCEL */
  796. /**
  797. * efx_filter_is_mc_recipient - test whether spec is a multicast recipient
  798. * @spec: Specification to test
  799. *
  800. * Return: %true if the specification is a non-drop RX filter that
  801. * matches a local MAC address I/G bit value of 1 or matches a local
  802. * IPv4 or IPv6 address value in the respective multicast address
  803. * range. Otherwise %false.
  804. */
  805. bool efx_filter_is_mc_recipient(const struct efx_filter_spec *spec)
  806. {
  807. if (!(spec->flags & EFX_FILTER_FLAG_RX) ||
  808. spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP)
  809. return false;
  810. if (spec->match_flags &
  811. (EFX_FILTER_MATCH_LOC_MAC | EFX_FILTER_MATCH_LOC_MAC_IG) &&
  812. is_multicast_ether_addr(spec->loc_mac))
  813. return true;
  814. if ((spec->match_flags &
  815. (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) ==
  816. (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) {
  817. if (spec->ether_type == htons(ETH_P_IP) &&
  818. ipv4_is_multicast(spec->loc_host[0]))
  819. return true;
  820. if (spec->ether_type == htons(ETH_P_IPV6) &&
  821. ((const u8 *)spec->loc_host)[0] == 0xff)
  822. return true;
  823. }
  824. return false;
  825. }