s5c73m3.h 14 KB

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  1. /*
  2. * Samsung LSI S5C73M3 8M pixel camera driver
  3. *
  4. * Copyright (C) 2012, Samsung Electronics, Co., Ltd.
  5. * Sylwester Nawrocki <s.nawrocki@samsung.com>
  6. * Andrzej Hajda <a.hajda@samsung.com>
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License
  10. * version 2 as published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. */
  17. #ifndef S5C73M3_H_
  18. #define S5C73M3_H_
  19. #include <linux/clk.h>
  20. #include <linux/kernel.h>
  21. #include <linux/regulator/consumer.h>
  22. #include <media/v4l2-common.h>
  23. #include <media/v4l2-ctrls.h>
  24. #include <media/v4l2-subdev.h>
  25. #include <media/i2c/s5c73m3.h>
  26. #define DRIVER_NAME "S5C73M3"
  27. #define S5C73M3_ISP_FMT MEDIA_BUS_FMT_VYUY8_2X8
  28. #define S5C73M3_JPEG_FMT MEDIA_BUS_FMT_S5C_UYVY_JPEG_1X8
  29. /* Subdevs pad index definitions */
  30. enum s5c73m3_pads {
  31. S5C73M3_ISP_PAD,
  32. S5C73M3_JPEG_PAD,
  33. S5C73M3_NUM_PADS
  34. };
  35. enum s5c73m3_oif_pads {
  36. OIF_ISP_PAD,
  37. OIF_JPEG_PAD,
  38. OIF_SOURCE_PAD,
  39. OIF_NUM_PADS
  40. };
  41. #define S5C73M3_SENSOR_FW_LEN 6
  42. #define S5C73M3_SENSOR_TYPE_LEN 12
  43. #define S5C73M3_REG(_addrh, _addrl) (((_addrh) << 16) | _addrl)
  44. #define AHB_MSB_ADDR_PTR 0xfcfc
  45. #define REG_CMDWR_ADDRH 0x0050
  46. #define REG_CMDWR_ADDRL 0x0054
  47. #define REG_CMDRD_ADDRH 0x0058
  48. #define REG_CMDRD_ADDRL 0x005c
  49. #define REG_CMDBUF_ADDR 0x0f14
  50. #define REG_I2C_SEQ_STATUS S5C73M3_REG(0x0009, 0x59A6)
  51. #define SEQ_END_PLL (1<<0x0)
  52. #define SEQ_END_SENSOR (1<<0x1)
  53. #define SEQ_END_GPIO (1<<0x2)
  54. #define SEQ_END_FROM (1<<0x3)
  55. #define SEQ_END_STABLE_AE_AWB (1<<0x4)
  56. #define SEQ_END_READY_I2C_CMD (1<<0x5)
  57. #define REG_I2C_STATUS S5C73M3_REG(0x0009, 0x599E)
  58. #define I2C_STATUS_CIS_I2C (1<<0x0)
  59. #define I2C_STATUS_AF_INIT (1<<0x1)
  60. #define I2C_STATUS_CAL_DATA (1<<0x2)
  61. #define I2C_STATUS_FRAME_COUNT (1<<0x3)
  62. #define I2C_STATUS_FROM_INIT (1<<0x4)
  63. #define I2C_STATUS_I2C_CIS_STREAM_OFF (1<<0x5)
  64. #define I2C_STATUS_I2C_N_CMD_OVER (1<<0x6)
  65. #define I2C_STATUS_I2C_N_CMD_MISMATCH (1<<0x7)
  66. #define I2C_STATUS_CHECK_BIN_CRC (1<<0x8)
  67. #define I2C_STATUS_EXCEPTION (1<<0x9)
  68. #define I2C_STATUS_INIF_INIT_STATE (0x8)
  69. #define REG_STATUS S5C73M3_REG(0x0009, 0x5080)
  70. #define REG_STATUS_BOOT_SUB_MAIN_ENTER 0xff01
  71. #define REG_STATUS_BOOT_SRAM_TIMING_OK 0xff02
  72. #define REG_STATUS_BOOT_INTERRUPTS_EN 0xff03
  73. #define REG_STATUS_BOOT_R_PLL_DONE 0xff04
  74. #define REG_STATUS_BOOT_R_PLL_LOCKTIME_DONE 0xff05
  75. #define REG_STATUS_BOOT_DELAY_COUNT_DONE 0xff06
  76. #define REG_STATUS_BOOT_I_PLL_DONE 0xff07
  77. #define REG_STATUS_BOOT_I_PLL_LOCKTIME_DONE 0xff08
  78. #define REG_STATUS_BOOT_PLL_INIT_OK 0xff09
  79. #define REG_STATUS_BOOT_SENSOR_INIT_OK 0xff0a
  80. #define REG_STATUS_BOOT_GPIO_SETTING_OK 0xff0b
  81. #define REG_STATUS_BOOT_READ_CAL_DATA_OK 0xff0c
  82. #define REG_STATUS_BOOT_STABLE_AE_AWB_OK 0xff0d
  83. #define REG_STATUS_ISP_COMMAND_COMPLETED 0xffff
  84. #define REG_STATUS_EXCEPTION_OCCURED 0xdead
  85. #define COMM_RESULT_OFFSET S5C73M3_REG(0x0009, 0x5000)
  86. #define COMM_IMG_OUTPUT 0x0902
  87. #define COMM_IMG_OUTPUT_HDR 0x0008
  88. #define COMM_IMG_OUTPUT_YUV 0x0009
  89. #define COMM_IMG_OUTPUT_INTERLEAVED 0x000d
  90. #define COMM_STILL_PRE_FLASH 0x0a00
  91. #define COMM_STILL_PRE_FLASH_FIRE 0x0000
  92. #define COMM_STILL_PRE_FLASH_NON_FIRED 0x0000
  93. #define COMM_STILL_PRE_FLASH_FIRED 0x0001
  94. #define COMM_STILL_MAIN_FLASH 0x0a02
  95. #define COMM_STILL_MAIN_FLASH_CANCEL 0x0001
  96. #define COMM_STILL_MAIN_FLASH_FIRE 0x0002
  97. #define COMM_ZOOM_STEP 0x0b00
  98. #define COMM_IMAGE_EFFECT 0x0b0a
  99. #define COMM_IMAGE_EFFECT_NONE 0x0001
  100. #define COMM_IMAGE_EFFECT_NEGATIVE 0x0002
  101. #define COMM_IMAGE_EFFECT_AQUA 0x0003
  102. #define COMM_IMAGE_EFFECT_SEPIA 0x0004
  103. #define COMM_IMAGE_EFFECT_MONO 0x0005
  104. #define COMM_IMAGE_QUALITY 0x0b0c
  105. #define COMM_IMAGE_QUALITY_SUPERFINE 0x0000
  106. #define COMM_IMAGE_QUALITY_FINE 0x0001
  107. #define COMM_IMAGE_QUALITY_NORMAL 0x0002
  108. #define COMM_FLASH_MODE 0x0b0e
  109. #define COMM_FLASH_MODE_OFF 0x0000
  110. #define COMM_FLASH_MODE_ON 0x0001
  111. #define COMM_FLASH_MODE_AUTO 0x0002
  112. #define COMM_FLASH_STATUS 0x0b80
  113. #define COMM_FLASH_STATUS_OFF 0x0001
  114. #define COMM_FLASH_STATUS_ON 0x0002
  115. #define COMM_FLASH_STATUS_AUTO 0x0003
  116. #define COMM_FLASH_TORCH 0x0b12
  117. #define COMM_FLASH_TORCH_OFF 0x0000
  118. #define COMM_FLASH_TORCH_ON 0x0001
  119. #define COMM_AE_NEEDS_FLASH 0x0cba
  120. #define COMM_AE_NEEDS_FLASH_OFF 0x0000
  121. #define COMM_AE_NEEDS_FLASH_ON 0x0001
  122. #define COMM_CHG_MODE 0x0b10
  123. #define COMM_CHG_MODE_NEW 0x8000
  124. #define COMM_CHG_MODE_SUBSAMPLING_HALF 0x2000
  125. #define COMM_CHG_MODE_SUBSAMPLING_QUARTER 0x4000
  126. #define COMM_CHG_MODE_YUV_320_240 0x0001
  127. #define COMM_CHG_MODE_YUV_640_480 0x0002
  128. #define COMM_CHG_MODE_YUV_880_720 0x0003
  129. #define COMM_CHG_MODE_YUV_960_720 0x0004
  130. #define COMM_CHG_MODE_YUV_1184_666 0x0005
  131. #define COMM_CHG_MODE_YUV_1280_720 0x0006
  132. #define COMM_CHG_MODE_YUV_1536_864 0x0007
  133. #define COMM_CHG_MODE_YUV_1600_1200 0x0008
  134. #define COMM_CHG_MODE_YUV_1632_1224 0x0009
  135. #define COMM_CHG_MODE_YUV_1920_1080 0x000a
  136. #define COMM_CHG_MODE_YUV_1920_1440 0x000b
  137. #define COMM_CHG_MODE_YUV_2304_1296 0x000c
  138. #define COMM_CHG_MODE_YUV_3264_2448 0x000d
  139. #define COMM_CHG_MODE_YUV_352_288 0x000e
  140. #define COMM_CHG_MODE_YUV_1008_672 0x000f
  141. #define COMM_CHG_MODE_JPEG_640_480 0x0010
  142. #define COMM_CHG_MODE_JPEG_800_450 0x0020
  143. #define COMM_CHG_MODE_JPEG_800_600 0x0030
  144. #define COMM_CHG_MODE_JPEG_1280_720 0x0040
  145. #define COMM_CHG_MODE_JPEG_1280_960 0x0050
  146. #define COMM_CHG_MODE_JPEG_1600_900 0x0060
  147. #define COMM_CHG_MODE_JPEG_1600_1200 0x0070
  148. #define COMM_CHG_MODE_JPEG_2048_1152 0x0080
  149. #define COMM_CHG_MODE_JPEG_2048_1536 0x0090
  150. #define COMM_CHG_MODE_JPEG_2560_1440 0x00a0
  151. #define COMM_CHG_MODE_JPEG_2560_1920 0x00b0
  152. #define COMM_CHG_MODE_JPEG_3264_2176 0x00c0
  153. #define COMM_CHG_MODE_JPEG_1024_768 0x00d0
  154. #define COMM_CHG_MODE_JPEG_3264_1836 0x00e0
  155. #define COMM_CHG_MODE_JPEG_3264_2448 0x00f0
  156. #define COMM_AF_CON 0x0e00
  157. #define COMM_AF_CON_STOP 0x0000
  158. #define COMM_AF_CON_SCAN 0x0001 /* Full Search */
  159. #define COMM_AF_CON_START 0x0002 /* Fast Search */
  160. #define COMM_AF_CAL 0x0e06
  161. #define COMM_AF_TOUCH_AF 0x0e0a
  162. #define REG_AF_STATUS S5C73M3_REG(0x0009, 0x5e80)
  163. #define REG_CAF_STATUS_FIND_SEARCH_DIR 0x0001
  164. #define REG_CAF_STATUS_FOCUSING 0x0002
  165. #define REG_CAF_STATUS_FOCUSED 0x0003
  166. #define REG_CAF_STATUS_UNFOCUSED 0x0004
  167. #define REG_AF_STATUS_INVALID 0x0010
  168. #define REG_AF_STATUS_FOCUSING 0x0020
  169. #define REG_AF_STATUS_FOCUSED 0x0030
  170. #define REG_AF_STATUS_UNFOCUSED 0x0040
  171. #define REG_AF_TOUCH_POSITION S5C73M3_REG(0x0009, 0x5e8e)
  172. #define COMM_AF_FACE_ZOOM 0x0e10
  173. #define COMM_AF_MODE 0x0e02
  174. #define COMM_AF_MODE_NORMAL 0x0000
  175. #define COMM_AF_MODE_MACRO 0x0001
  176. #define COMM_AF_MODE_MOVIE_CAF_START 0x0002
  177. #define COMM_AF_MODE_MOVIE_CAF_STOP 0x0003
  178. #define COMM_AF_MODE_PREVIEW_CAF_START 0x0004
  179. #define COMM_AF_MODE_PREVIEW_CAF_STOP 0x0005
  180. #define COMM_AF_SOFTLANDING 0x0e16
  181. #define COMM_AF_SOFTLANDING_ON 0x0000
  182. #define COMM_AF_SOFTLANDING_RES_COMPLETE 0x0001
  183. #define COMM_FACE_DET 0x0e0c
  184. #define COMM_FACE_DET_OFF 0x0000
  185. #define COMM_FACE_DET_ON 0x0001
  186. #define COMM_FACE_DET_OSD 0x0e0e
  187. #define COMM_FACE_DET_OSD_OFF 0x0000
  188. #define COMM_FACE_DET_OSD_ON 0x0001
  189. #define COMM_AE_CON 0x0c00
  190. #define COMM_AE_STOP 0x0000 /* lock */
  191. #define COMM_AE_START 0x0001 /* unlock */
  192. #define COMM_ISO 0x0c02
  193. #define COMM_ISO_AUTO 0x0000
  194. #define COMM_ISO_100 0x0001
  195. #define COMM_ISO_200 0x0002
  196. #define COMM_ISO_400 0x0003
  197. #define COMM_ISO_800 0x0004
  198. #define COMM_ISO_SPORTS 0x0005
  199. #define COMM_ISO_NIGHT 0x0006
  200. #define COMM_ISO_INDOOR 0x0007
  201. /* 0x00000 (-2.0 EV)...0x0008 (2.0 EV), 0.5EV step */
  202. #define COMM_EV 0x0c04
  203. #define COMM_METERING 0x0c06
  204. #define COMM_METERING_CENTER 0x0000
  205. #define COMM_METERING_SPOT 0x0001
  206. #define COMM_METERING_AVERAGE 0x0002
  207. #define COMM_METERING_SMART 0x0003
  208. #define COMM_WDR 0x0c08
  209. #define COMM_WDR_OFF 0x0000
  210. #define COMM_WDR_ON 0x0001
  211. #define COMM_FLICKER_MODE 0x0c12
  212. #define COMM_FLICKER_NONE 0x0000
  213. #define COMM_FLICKER_MANUAL_50HZ 0x0001
  214. #define COMM_FLICKER_MANUAL_60HZ 0x0002
  215. #define COMM_FLICKER_AUTO 0x0003
  216. #define COMM_FLICKER_AUTO_50HZ 0x0004
  217. #define COMM_FLICKER_AUTO_60HZ 0x0005
  218. #define COMM_FRAME_RATE 0x0c1e
  219. #define COMM_FRAME_RATE_AUTO_SET 0x0000
  220. #define COMM_FRAME_RATE_FIXED_30FPS 0x0002
  221. #define COMM_FRAME_RATE_FIXED_20FPS 0x0003
  222. #define COMM_FRAME_RATE_FIXED_15FPS 0x0004
  223. #define COMM_FRAME_RATE_FIXED_60FPS 0x0007
  224. #define COMM_FRAME_RATE_FIXED_120FPS 0x0008
  225. #define COMM_FRAME_RATE_FIXED_7FPS 0x0009
  226. #define COMM_FRAME_RATE_FIXED_10FPS 0x000a
  227. #define COMM_FRAME_RATE_FIXED_90FPS 0x000b
  228. #define COMM_FRAME_RATE_ANTI_SHAKE 0x0013
  229. /* 0x0000...0x0004 -> sharpness: 0, 1, 2, -1, -2 */
  230. #define COMM_SHARPNESS 0x0c14
  231. /* 0x0000...0x0004 -> saturation: 0, 1, 2, -1, -2 */
  232. #define COMM_SATURATION 0x0c16
  233. /* 0x0000...0x0004 -> contrast: 0, 1, 2, -1, -2 */
  234. #define COMM_CONTRAST 0x0c18
  235. #define COMM_SCENE_MODE 0x0c1a
  236. #define COMM_SCENE_MODE_NONE 0x0000
  237. #define COMM_SCENE_MODE_PORTRAIT 0x0001
  238. #define COMM_SCENE_MODE_LANDSCAPE 0x0002
  239. #define COMM_SCENE_MODE_SPORTS 0x0003
  240. #define COMM_SCENE_MODE_INDOOR 0x0004
  241. #define COMM_SCENE_MODE_BEACH 0x0005
  242. #define COMM_SCENE_MODE_SUNSET 0x0006
  243. #define COMM_SCENE_MODE_DAWN 0x0007
  244. #define COMM_SCENE_MODE_FALL 0x0008
  245. #define COMM_SCENE_MODE_NIGHT 0x0009
  246. #define COMM_SCENE_MODE_AGAINST_LIGHT 0x000a
  247. #define COMM_SCENE_MODE_FIRE 0x000b
  248. #define COMM_SCENE_MODE_TEXT 0x000c
  249. #define COMM_SCENE_MODE_CANDLE 0x000d
  250. #define COMM_AE_AUTO_BRACKET 0x0b14
  251. #define COMM_AE_AUTO_BRAKET_EV05 0x0080
  252. #define COMM_AE_AUTO_BRAKET_EV10 0x0100
  253. #define COMM_AE_AUTO_BRAKET_EV15 0x0180
  254. #define COMM_AE_AUTO_BRAKET_EV20 0x0200
  255. #define COMM_SENSOR_STREAMING 0x090a
  256. #define COMM_SENSOR_STREAMING_OFF 0x0000
  257. #define COMM_SENSOR_STREAMING_ON 0x0001
  258. #define COMM_AWB_MODE 0x0d02
  259. #define COMM_AWB_MODE_INCANDESCENT 0x0000
  260. #define COMM_AWB_MODE_FLUORESCENT1 0x0001
  261. #define COMM_AWB_MODE_FLUORESCENT2 0x0002
  262. #define COMM_AWB_MODE_DAYLIGHT 0x0003
  263. #define COMM_AWB_MODE_CLOUDY 0x0004
  264. #define COMM_AWB_MODE_AUTO 0x0005
  265. #define COMM_AWB_CON 0x0d00
  266. #define COMM_AWB_STOP 0x0000 /* lock */
  267. #define COMM_AWB_START 0x0001 /* unlock */
  268. #define COMM_FW_UPDATE 0x0906
  269. #define COMM_FW_UPDATE_NOT_READY 0x0000
  270. #define COMM_FW_UPDATE_SUCCESS 0x0005
  271. #define COMM_FW_UPDATE_FAIL 0x0007
  272. #define COMM_FW_UPDATE_BUSY 0xffff
  273. #define S5C73M3_MAX_SUPPLIES 6
  274. #define S5C73M3_DEFAULT_MCLK_FREQ 24000000U
  275. struct s5c73m3_ctrls {
  276. struct v4l2_ctrl_handler handler;
  277. struct {
  278. /* exposure/exposure bias cluster */
  279. struct v4l2_ctrl *auto_exposure;
  280. struct v4l2_ctrl *exposure_bias;
  281. struct v4l2_ctrl *exposure_metering;
  282. };
  283. struct {
  284. /* iso/auto iso cluster */
  285. struct v4l2_ctrl *auto_iso;
  286. struct v4l2_ctrl *iso;
  287. };
  288. struct v4l2_ctrl *auto_wb;
  289. struct {
  290. /* continuous auto focus/auto focus cluster */
  291. struct v4l2_ctrl *focus_auto;
  292. struct v4l2_ctrl *af_start;
  293. struct v4l2_ctrl *af_stop;
  294. struct v4l2_ctrl *af_status;
  295. struct v4l2_ctrl *af_distance;
  296. };
  297. struct v4l2_ctrl *aaa_lock;
  298. struct v4l2_ctrl *colorfx;
  299. struct v4l2_ctrl *contrast;
  300. struct v4l2_ctrl *saturation;
  301. struct v4l2_ctrl *sharpness;
  302. struct v4l2_ctrl *zoom;
  303. struct v4l2_ctrl *wdr;
  304. struct v4l2_ctrl *stabilization;
  305. struct v4l2_ctrl *jpeg_quality;
  306. struct v4l2_ctrl *scene_mode;
  307. };
  308. enum s5c73m3_gpio_id {
  309. STBY,
  310. RST,
  311. GPIO_NUM,
  312. };
  313. enum s5c73m3_resolution_types {
  314. RES_ISP,
  315. RES_JPEG,
  316. };
  317. struct s5c73m3_interval {
  318. u16 fps_reg;
  319. struct v4l2_fract interval;
  320. /* Maximum rectangle for the interval */
  321. struct v4l2_frmsize_discrete size;
  322. };
  323. struct s5c73m3 {
  324. struct v4l2_subdev sensor_sd;
  325. struct media_pad sensor_pads[S5C73M3_NUM_PADS];
  326. struct v4l2_subdev oif_sd;
  327. struct media_pad oif_pads[OIF_NUM_PADS];
  328. struct spi_driver spidrv;
  329. struct spi_device *spi_dev;
  330. struct i2c_client *i2c_client;
  331. u32 i2c_write_address;
  332. u32 i2c_read_address;
  333. struct regulator_bulk_data supplies[S5C73M3_MAX_SUPPLIES];
  334. struct s5c73m3_gpio gpio[GPIO_NUM];
  335. struct clk *clock;
  336. /* External master clock frequency */
  337. u32 mclk_frequency;
  338. /* Video bus type - MIPI-CSI2/parallel */
  339. enum v4l2_mbus_type bus_type;
  340. const struct s5c73m3_frame_size *sensor_pix_size[2];
  341. const struct s5c73m3_frame_size *oif_pix_size[2];
  342. u32 mbus_code;
  343. const struct s5c73m3_interval *fiv;
  344. struct v4l2_mbus_frame_desc frame_desc;
  345. /* protects the struct members below */
  346. struct mutex lock;
  347. struct s5c73m3_ctrls ctrls;
  348. u8 streaming:1;
  349. u8 apply_fmt:1;
  350. u8 apply_fiv:1;
  351. u8 isp_ready:1;
  352. short power;
  353. char sensor_fw[S5C73M3_SENSOR_FW_LEN + 2];
  354. char sensor_type[S5C73M3_SENSOR_TYPE_LEN + 2];
  355. char fw_file_version[2];
  356. unsigned int fw_size;
  357. };
  358. struct s5c73m3_frame_size {
  359. u32 width;
  360. u32 height;
  361. u8 reg_val;
  362. };
  363. extern int s5c73m3_dbg;
  364. int s5c73m3_register_spi_driver(struct s5c73m3 *state);
  365. void s5c73m3_unregister_spi_driver(struct s5c73m3 *state);
  366. int s5c73m3_spi_write(struct s5c73m3 *state, const void *addr,
  367. const unsigned int len, const unsigned int tx_size);
  368. int s5c73m3_spi_read(struct s5c73m3 *state, void *addr,
  369. const unsigned int len, const unsigned int tx_size);
  370. int s5c73m3_read(struct s5c73m3 *state, u32 addr, u16 *data);
  371. int s5c73m3_write(struct s5c73m3 *state, u32 addr, u16 data);
  372. int s5c73m3_isp_command(struct s5c73m3 *state, u16 command, u16 data);
  373. int s5c73m3_init_controls(struct s5c73m3 *state);
  374. static inline struct v4l2_subdev *ctrl_to_sensor_sd(struct v4l2_ctrl *ctrl)
  375. {
  376. return &container_of(ctrl->handler, struct s5c73m3,
  377. ctrls.handler)->sensor_sd;
  378. }
  379. static inline struct s5c73m3 *sensor_sd_to_s5c73m3(struct v4l2_subdev *sd)
  380. {
  381. return container_of(sd, struct s5c73m3, sensor_sd);
  382. }
  383. static inline struct s5c73m3 *oif_sd_to_s5c73m3(struct v4l2_subdev *sd)
  384. {
  385. return container_of(sd, struct s5c73m3, oif_sd);
  386. }
  387. #endif /* S5C73M3_H_ */