horus3a.c 10 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410
  1. /*
  2. * horus3a.h
  3. *
  4. * Sony Horus3A DVB-S/S2 tuner driver
  5. *
  6. * Copyright 2012 Sony Corporation
  7. * Copyright (C) 2014 NetUP Inc.
  8. * Copyright (C) 2014 Sergey Kozlov <serjk@netup.ru>
  9. * Copyright (C) 2014 Abylay Ospan <aospan@netup.ru>
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License as published by
  13. * the Free Software Foundation; either version 2 of the License, or
  14. * (at your option) any later version.
  15. *
  16. * This program is distributed in the hope that it will be useful,
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19. * GNU General Public License for more details.
  20. */
  21. #include <linux/slab.h>
  22. #include <linux/module.h>
  23. #include <linux/dvb/frontend.h>
  24. #include <linux/types.h>
  25. #include "horus3a.h"
  26. #include "dvb_frontend.h"
  27. #define MAX_WRITE_REGSIZE 5
  28. enum horus3a_state {
  29. STATE_UNKNOWN,
  30. STATE_SLEEP,
  31. STATE_ACTIVE
  32. };
  33. struct horus3a_priv {
  34. u32 frequency;
  35. u8 i2c_address;
  36. struct i2c_adapter *i2c;
  37. enum horus3a_state state;
  38. void *set_tuner_data;
  39. int (*set_tuner)(void *, int);
  40. };
  41. static void horus3a_i2c_debug(struct horus3a_priv *priv,
  42. u8 reg, u8 write, const u8 *data, u32 len)
  43. {
  44. dev_dbg(&priv->i2c->dev, "horus3a: I2C %s reg 0x%02x size %d\n",
  45. (write == 0 ? "read" : "write"), reg, len);
  46. print_hex_dump_bytes("horus3a: I2C data: ",
  47. DUMP_PREFIX_OFFSET, data, len);
  48. }
  49. static int horus3a_write_regs(struct horus3a_priv *priv,
  50. u8 reg, const u8 *data, u32 len)
  51. {
  52. int ret;
  53. u8 buf[MAX_WRITE_REGSIZE + 1];
  54. struct i2c_msg msg[1] = {
  55. {
  56. .addr = priv->i2c_address,
  57. .flags = 0,
  58. .len = len + 1,
  59. .buf = buf,
  60. }
  61. };
  62. if (len + 1 > sizeof(buf)) {
  63. dev_warn(&priv->i2c->dev,"wr reg=%04x: len=%d is too big!\n",
  64. reg, len + 1);
  65. return -E2BIG;
  66. }
  67. horus3a_i2c_debug(priv, reg, 1, data, len);
  68. buf[0] = reg;
  69. memcpy(&buf[1], data, len);
  70. ret = i2c_transfer(priv->i2c, msg, 1);
  71. if (ret >= 0 && ret != 1)
  72. ret = -EREMOTEIO;
  73. if (ret < 0) {
  74. dev_warn(&priv->i2c->dev,
  75. "%s: i2c wr failed=%d reg=%02x len=%d\n",
  76. KBUILD_MODNAME, ret, reg, len);
  77. return ret;
  78. }
  79. return 0;
  80. }
  81. static int horus3a_write_reg(struct horus3a_priv *priv, u8 reg, u8 val)
  82. {
  83. return horus3a_write_regs(priv, reg, &val, 1);
  84. }
  85. static int horus3a_enter_power_save(struct horus3a_priv *priv)
  86. {
  87. u8 data[2];
  88. dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
  89. if (priv->state == STATE_SLEEP)
  90. return 0;
  91. /* IQ Generator disable */
  92. horus3a_write_reg(priv, 0x2a, 0x79);
  93. /* MDIV_EN = 0 */
  94. horus3a_write_reg(priv, 0x29, 0x70);
  95. /* VCO disable preparation */
  96. horus3a_write_reg(priv, 0x28, 0x3e);
  97. /* VCO buffer disable */
  98. horus3a_write_reg(priv, 0x2a, 0x19);
  99. /* VCO calibration disable */
  100. horus3a_write_reg(priv, 0x1c, 0x00);
  101. /* Power save setting (xtal is not stopped) */
  102. data[0] = 0xC0;
  103. /* LNA is Disabled */
  104. data[1] = 0xA7;
  105. /* 0x11 - 0x12 */
  106. horus3a_write_regs(priv, 0x11, data, sizeof(data));
  107. priv->state = STATE_SLEEP;
  108. return 0;
  109. }
  110. static int horus3a_leave_power_save(struct horus3a_priv *priv)
  111. {
  112. u8 data[2];
  113. dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
  114. if (priv->state == STATE_ACTIVE)
  115. return 0;
  116. /* Leave power save */
  117. data[0] = 0x00;
  118. /* LNA is Disabled */
  119. data[1] = 0xa7;
  120. /* 0x11 - 0x12 */
  121. horus3a_write_regs(priv, 0x11, data, sizeof(data));
  122. /* VCO buffer enable */
  123. horus3a_write_reg(priv, 0x2a, 0x79);
  124. /* VCO calibration enable */
  125. horus3a_write_reg(priv, 0x1c, 0xc0);
  126. /* MDIV_EN = 1 */
  127. horus3a_write_reg(priv, 0x29, 0x71);
  128. usleep_range(5000, 7000);
  129. priv->state = STATE_ACTIVE;
  130. return 0;
  131. }
  132. static int horus3a_init(struct dvb_frontend *fe)
  133. {
  134. struct horus3a_priv *priv = fe->tuner_priv;
  135. dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
  136. return 0;
  137. }
  138. static int horus3a_release(struct dvb_frontend *fe)
  139. {
  140. struct horus3a_priv *priv = fe->tuner_priv;
  141. dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
  142. kfree(fe->tuner_priv);
  143. fe->tuner_priv = NULL;
  144. return 0;
  145. }
  146. static int horus3a_sleep(struct dvb_frontend *fe)
  147. {
  148. struct horus3a_priv *priv = fe->tuner_priv;
  149. dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
  150. horus3a_enter_power_save(priv);
  151. return 0;
  152. }
  153. static int horus3a_set_params(struct dvb_frontend *fe)
  154. {
  155. struct dtv_frontend_properties *p = &fe->dtv_property_cache;
  156. struct horus3a_priv *priv = fe->tuner_priv;
  157. u32 frequency = p->frequency;
  158. u32 symbol_rate = p->symbol_rate/1000;
  159. u8 mixdiv = 0;
  160. u8 mdiv = 0;
  161. u32 ms = 0;
  162. u8 f_ctl = 0;
  163. u8 g_ctl = 0;
  164. u8 fc_lpf = 0;
  165. u8 data[5];
  166. dev_dbg(&priv->i2c->dev, "%s(): frequency %dkHz symbol_rate %dksps\n",
  167. __func__, frequency, symbol_rate);
  168. if (priv->set_tuner)
  169. priv->set_tuner(priv->set_tuner_data, 0);
  170. if (priv->state == STATE_SLEEP)
  171. horus3a_leave_power_save(priv);
  172. /* frequency should be X MHz (X : integer) */
  173. frequency = DIV_ROUND_CLOSEST(frequency, 1000) * 1000;
  174. if (frequency <= 1155000) {
  175. mixdiv = 4;
  176. mdiv = 1;
  177. } else {
  178. mixdiv = 2;
  179. mdiv = 0;
  180. }
  181. /* Assumed that fREF == 1MHz (1000kHz) */
  182. ms = DIV_ROUND_CLOSEST((frequency * mixdiv) / 2, 1000);
  183. if (ms > 0x7FFF) { /* 15 bit */
  184. dev_err(&priv->i2c->dev, "horus3a: invalid frequency %d\n",
  185. frequency);
  186. return -EINVAL;
  187. }
  188. if (frequency < 975000) {
  189. /* F_CTL=11100 G_CTL=001 */
  190. f_ctl = 0x1C;
  191. g_ctl = 0x01;
  192. } else if (frequency < 1050000) {
  193. /* F_CTL=11000 G_CTL=010 */
  194. f_ctl = 0x18;
  195. g_ctl = 0x02;
  196. } else if (frequency < 1150000) {
  197. /* F_CTL=10100 G_CTL=010 */
  198. f_ctl = 0x14;
  199. g_ctl = 0x02;
  200. } else if (frequency < 1250000) {
  201. /* F_CTL=10000 G_CTL=011 */
  202. f_ctl = 0x10;
  203. g_ctl = 0x03;
  204. } else if (frequency < 1350000) {
  205. /* F_CTL=01100 G_CTL=100 */
  206. f_ctl = 0x0C;
  207. g_ctl = 0x04;
  208. } else if (frequency < 1450000) {
  209. /* F_CTL=01010 G_CTL=100 */
  210. f_ctl = 0x0A;
  211. g_ctl = 0x04;
  212. } else if (frequency < 1600000) {
  213. /* F_CTL=00111 G_CTL=101 */
  214. f_ctl = 0x07;
  215. g_ctl = 0x05;
  216. } else if (frequency < 1800000) {
  217. /* F_CTL=00100 G_CTL=010 */
  218. f_ctl = 0x04;
  219. g_ctl = 0x02;
  220. } else if (frequency < 2000000) {
  221. /* F_CTL=00010 G_CTL=001 */
  222. f_ctl = 0x02;
  223. g_ctl = 0x01;
  224. } else {
  225. /* F_CTL=00000 G_CTL=000 */
  226. f_ctl = 0x00;
  227. g_ctl = 0x00;
  228. }
  229. /* LPF cutoff frequency setting */
  230. if (p->delivery_system == SYS_DVBS) {
  231. /*
  232. * rolloff = 0.35
  233. * SR <= 4.3
  234. * fc_lpf = 5
  235. * 4.3 < SR <= 10
  236. * fc_lpf = SR * (1 + rolloff) / 2 + SR / 2 =
  237. * SR * 1.175 = SR * (47/40)
  238. * 10 < SR
  239. * fc_lpf = SR * (1 + rolloff) / 2 + 5 =
  240. * SR * 0.675 + 5 = SR * (27/40) + 5
  241. * NOTE: The result should be round up.
  242. */
  243. if (symbol_rate <= 4300)
  244. fc_lpf = 5;
  245. else if (symbol_rate <= 10000)
  246. fc_lpf = (u8)DIV_ROUND_UP(symbol_rate * 47, 40000);
  247. else
  248. fc_lpf = (u8)DIV_ROUND_UP(symbol_rate * 27, 40000) + 5;
  249. /* 5 <= fc_lpf <= 36 */
  250. if (fc_lpf > 36)
  251. fc_lpf = 36;
  252. } else if (p->delivery_system == SYS_DVBS2) {
  253. /*
  254. * SR <= 4.5:
  255. * fc_lpf = 5
  256. * 4.5 < SR <= 10:
  257. * fc_lpf = SR * (1 + rolloff) / 2 + SR / 2
  258. * 10 < SR:
  259. * fc_lpf = SR * (1 + rolloff) / 2 + 5
  260. * NOTE: The result should be round up.
  261. */
  262. if (symbol_rate <= 4500)
  263. fc_lpf = 5;
  264. else if (symbol_rate <= 10000)
  265. fc_lpf = (u8)((symbol_rate * 11 + (10000-1)) / 10000);
  266. else
  267. fc_lpf = (u8)((symbol_rate * 3 + (5000-1)) / 5000 + 5);
  268. /* 5 <= fc_lpf <= 36 is valid */
  269. if (fc_lpf > 36)
  270. fc_lpf = 36;
  271. } else {
  272. dev_err(&priv->i2c->dev,
  273. "horus3a: invalid delivery system %d\n",
  274. p->delivery_system);
  275. return -EINVAL;
  276. }
  277. /* 0x00 - 0x04 */
  278. data[0] = (u8)((ms >> 7) & 0xFF);
  279. data[1] = (u8)((ms << 1) & 0xFF);
  280. data[2] = 0x00;
  281. data[3] = 0x00;
  282. data[4] = (u8)(mdiv << 7);
  283. horus3a_write_regs(priv, 0x00, data, sizeof(data));
  284. /* Write G_CTL, F_CTL */
  285. horus3a_write_reg(priv, 0x09, (u8)((g_ctl << 5) | f_ctl));
  286. /* Write LPF cutoff frequency */
  287. horus3a_write_reg(priv, 0x37, (u8)(0x80 | (fc_lpf << 1)));
  288. /* Start Calibration */
  289. horus3a_write_reg(priv, 0x05, 0x80);
  290. /* IQ Generator enable */
  291. horus3a_write_reg(priv, 0x2a, 0x7b);
  292. /* tuner stabilization time */
  293. msleep(60);
  294. /* Store tuned frequency to the struct */
  295. priv->frequency = ms * 2 * 1000 / mixdiv;
  296. return 0;
  297. }
  298. static int horus3a_get_frequency(struct dvb_frontend *fe, u32 *frequency)
  299. {
  300. struct horus3a_priv *priv = fe->tuner_priv;
  301. *frequency = priv->frequency;
  302. return 0;
  303. }
  304. static const struct dvb_tuner_ops horus3a_tuner_ops = {
  305. .info = {
  306. .name = "Sony Horus3a",
  307. .frequency_min = 950000,
  308. .frequency_max = 2150000,
  309. .frequency_step = 1000,
  310. },
  311. .init = horus3a_init,
  312. .release = horus3a_release,
  313. .sleep = horus3a_sleep,
  314. .set_params = horus3a_set_params,
  315. .get_frequency = horus3a_get_frequency,
  316. };
  317. struct dvb_frontend *horus3a_attach(struct dvb_frontend *fe,
  318. const struct horus3a_config *config,
  319. struct i2c_adapter *i2c)
  320. {
  321. u8 buf[3], val;
  322. struct horus3a_priv *priv = NULL;
  323. priv = kzalloc(sizeof(struct horus3a_priv), GFP_KERNEL);
  324. if (priv == NULL)
  325. return NULL;
  326. priv->i2c_address = (config->i2c_address >> 1);
  327. priv->i2c = i2c;
  328. priv->set_tuner_data = config->set_tuner_priv;
  329. priv->set_tuner = config->set_tuner_callback;
  330. if (fe->ops.i2c_gate_ctrl)
  331. fe->ops.i2c_gate_ctrl(fe, 1);
  332. /* wait 4ms after power on */
  333. usleep_range(4000, 6000);
  334. /* IQ Generator disable */
  335. horus3a_write_reg(priv, 0x2a, 0x79);
  336. /* REF_R = Xtal Frequency */
  337. buf[0] = config->xtal_freq_mhz;
  338. buf[1] = config->xtal_freq_mhz;
  339. buf[2] = 0;
  340. /* 0x6 - 0x8 */
  341. horus3a_write_regs(priv, 0x6, buf, 3);
  342. /* IQ Out = Single Ended */
  343. horus3a_write_reg(priv, 0x0a, 0x40);
  344. switch (config->xtal_freq_mhz) {
  345. case 27:
  346. val = 0x1f;
  347. break;
  348. case 24:
  349. val = 0x10;
  350. break;
  351. case 16:
  352. val = 0xc;
  353. break;
  354. default:
  355. val = 0;
  356. dev_warn(&priv->i2c->dev,
  357. "horus3a: invalid xtal frequency %dMHz\n",
  358. config->xtal_freq_mhz);
  359. break;
  360. }
  361. val <<= 2;
  362. horus3a_write_reg(priv, 0x0e, val);
  363. horus3a_enter_power_save(priv);
  364. usleep_range(3000, 5000);
  365. if (fe->ops.i2c_gate_ctrl)
  366. fe->ops.i2c_gate_ctrl(fe, 0);
  367. memcpy(&fe->ops.tuner_ops, &horus3a_tuner_ops,
  368. sizeof(struct dvb_tuner_ops));
  369. fe->tuner_priv = priv;
  370. dev_info(&priv->i2c->dev,
  371. "Sony HORUS3A attached on addr=%x at I2C adapter %p\n",
  372. priv->i2c_address, priv->i2c);
  373. return fe;
  374. }
  375. EXPORT_SYMBOL(horus3a_attach);
  376. MODULE_DESCRIPTION("Sony HORUS3A sattelite tuner driver");
  377. MODULE_AUTHOR("Sergey Kozlov <serjk@netup.ru>");
  378. MODULE_LICENSE("GPL");