odp.c 23 KB

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  1. /*
  2. * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
  3. *
  4. * This software is available to you under a choice of one of two
  5. * licenses. You may choose to be licensed under the terms of the GNU
  6. * General Public License (GPL) Version 2, available from the file
  7. * COPYING in the main directory of this source tree, or the
  8. * OpenIB.org BSD license below:
  9. *
  10. * Redistribution and use in source and binary forms, with or
  11. * without modification, are permitted provided that the following
  12. * conditions are met:
  13. *
  14. * - Redistributions of source code must retain the above
  15. * copyright notice, this list of conditions and the following
  16. * disclaimer.
  17. *
  18. * - Redistributions in binary form must reproduce the above
  19. * copyright notice, this list of conditions and the following
  20. * disclaimer in the documentation and/or other materials
  21. * provided with the distribution.
  22. *
  23. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30. * SOFTWARE.
  31. */
  32. #include <rdma/ib_umem.h>
  33. #include <rdma/ib_umem_odp.h>
  34. #include "mlx5_ib.h"
  35. #define MAX_PREFETCH_LEN (4*1024*1024U)
  36. /* Timeout in ms to wait for an active mmu notifier to complete when handling
  37. * a pagefault. */
  38. #define MMU_NOTIFIER_TIMEOUT 1000
  39. struct workqueue_struct *mlx5_ib_page_fault_wq;
  40. void mlx5_ib_invalidate_range(struct ib_umem *umem, unsigned long start,
  41. unsigned long end)
  42. {
  43. struct mlx5_ib_mr *mr;
  44. const u64 umr_block_mask = (MLX5_UMR_MTT_ALIGNMENT / sizeof(u64)) - 1;
  45. u64 idx = 0, blk_start_idx = 0;
  46. int in_block = 0;
  47. u64 addr;
  48. if (!umem || !umem->odp_data) {
  49. pr_err("invalidation called on NULL umem or non-ODP umem\n");
  50. return;
  51. }
  52. mr = umem->odp_data->private;
  53. if (!mr || !mr->ibmr.pd)
  54. return;
  55. start = max_t(u64, ib_umem_start(umem), start);
  56. end = min_t(u64, ib_umem_end(umem), end);
  57. /*
  58. * Iteration one - zap the HW's MTTs. The notifiers_count ensures that
  59. * while we are doing the invalidation, no page fault will attempt to
  60. * overwrite the same MTTs. Concurent invalidations might race us,
  61. * but they will write 0s as well, so no difference in the end result.
  62. */
  63. for (addr = start; addr < end; addr += (u64)umem->page_size) {
  64. idx = (addr - ib_umem_start(umem)) / PAGE_SIZE;
  65. /*
  66. * Strive to write the MTTs in chunks, but avoid overwriting
  67. * non-existing MTTs. The huristic here can be improved to
  68. * estimate the cost of another UMR vs. the cost of bigger
  69. * UMR.
  70. */
  71. if (umem->odp_data->dma_list[idx] &
  72. (ODP_READ_ALLOWED_BIT | ODP_WRITE_ALLOWED_BIT)) {
  73. if (!in_block) {
  74. blk_start_idx = idx;
  75. in_block = 1;
  76. }
  77. } else {
  78. u64 umr_offset = idx & umr_block_mask;
  79. if (in_block && umr_offset == 0) {
  80. mlx5_ib_update_mtt(mr, blk_start_idx,
  81. idx - blk_start_idx, 1);
  82. in_block = 0;
  83. }
  84. }
  85. }
  86. if (in_block)
  87. mlx5_ib_update_mtt(mr, blk_start_idx, idx - blk_start_idx + 1,
  88. 1);
  89. /*
  90. * We are now sure that the device will not access the
  91. * memory. We can safely unmap it, and mark it as dirty if
  92. * needed.
  93. */
  94. ib_umem_odp_unmap_dma_pages(umem, start, end);
  95. }
  96. void mlx5_ib_internal_fill_odp_caps(struct mlx5_ib_dev *dev)
  97. {
  98. struct ib_odp_caps *caps = &dev->odp_caps;
  99. memset(caps, 0, sizeof(*caps));
  100. if (!MLX5_CAP_GEN(dev->mdev, pg))
  101. return;
  102. caps->general_caps = IB_ODP_SUPPORT;
  103. if (MLX5_CAP_ODP(dev->mdev, ud_odp_caps.send))
  104. caps->per_transport_caps.ud_odp_caps |= IB_ODP_SUPPORT_SEND;
  105. if (MLX5_CAP_ODP(dev->mdev, rc_odp_caps.send))
  106. caps->per_transport_caps.rc_odp_caps |= IB_ODP_SUPPORT_SEND;
  107. if (MLX5_CAP_ODP(dev->mdev, rc_odp_caps.receive))
  108. caps->per_transport_caps.rc_odp_caps |= IB_ODP_SUPPORT_RECV;
  109. if (MLX5_CAP_ODP(dev->mdev, rc_odp_caps.write))
  110. caps->per_transport_caps.rc_odp_caps |= IB_ODP_SUPPORT_WRITE;
  111. if (MLX5_CAP_ODP(dev->mdev, rc_odp_caps.read))
  112. caps->per_transport_caps.rc_odp_caps |= IB_ODP_SUPPORT_READ;
  113. return;
  114. }
  115. static struct mlx5_ib_mr *mlx5_ib_odp_find_mr_lkey(struct mlx5_ib_dev *dev,
  116. u32 key)
  117. {
  118. u32 base_key = mlx5_base_mkey(key);
  119. struct mlx5_core_mkey *mmkey = __mlx5_mr_lookup(dev->mdev, base_key);
  120. struct mlx5_ib_mr *mr = container_of(mmkey, struct mlx5_ib_mr, mmkey);
  121. if (!mmkey || mmkey->key != key || !mr->live)
  122. return NULL;
  123. return container_of(mmkey, struct mlx5_ib_mr, mmkey);
  124. }
  125. static void mlx5_ib_page_fault_resume(struct mlx5_ib_qp *qp,
  126. struct mlx5_ib_pfault *pfault,
  127. int error)
  128. {
  129. struct mlx5_ib_dev *dev = to_mdev(qp->ibqp.pd->device);
  130. u32 qpn = qp->trans_qp.base.mqp.qpn;
  131. int ret = mlx5_core_page_fault_resume(dev->mdev,
  132. qpn,
  133. pfault->mpfault.flags,
  134. error);
  135. if (ret)
  136. pr_err("Failed to resolve the page fault on QP 0x%x\n", qpn);
  137. }
  138. /*
  139. * Handle a single data segment in a page-fault WQE.
  140. *
  141. * Returns number of pages retrieved on success. The caller will continue to
  142. * the next data segment.
  143. * Can return the following error codes:
  144. * -EAGAIN to designate a temporary error. The caller will abort handling the
  145. * page fault and resolve it.
  146. * -EFAULT when there's an error mapping the requested pages. The caller will
  147. * abort the page fault handling and possibly move the QP to an error state.
  148. * On other errors the QP should also be closed with an error.
  149. */
  150. static int pagefault_single_data_segment(struct mlx5_ib_qp *qp,
  151. struct mlx5_ib_pfault *pfault,
  152. u32 key, u64 io_virt, size_t bcnt,
  153. u32 *bytes_mapped)
  154. {
  155. struct mlx5_ib_dev *mib_dev = to_mdev(qp->ibqp.pd->device);
  156. int srcu_key;
  157. unsigned int current_seq;
  158. u64 start_idx;
  159. int npages = 0, ret = 0;
  160. struct mlx5_ib_mr *mr;
  161. u64 access_mask = ODP_READ_ALLOWED_BIT;
  162. srcu_key = srcu_read_lock(&mib_dev->mr_srcu);
  163. mr = mlx5_ib_odp_find_mr_lkey(mib_dev, key);
  164. /*
  165. * If we didn't find the MR, it means the MR was closed while we were
  166. * handling the ODP event. In this case we return -EFAULT so that the
  167. * QP will be closed.
  168. */
  169. if (!mr || !mr->ibmr.pd) {
  170. pr_err("Failed to find relevant mr for lkey=0x%06x, probably the MR was destroyed\n",
  171. key);
  172. ret = -EFAULT;
  173. goto srcu_unlock;
  174. }
  175. if (!mr->umem->odp_data) {
  176. pr_debug("skipping non ODP MR (lkey=0x%06x) in page fault handler.\n",
  177. key);
  178. if (bytes_mapped)
  179. *bytes_mapped +=
  180. (bcnt - pfault->mpfault.bytes_committed);
  181. goto srcu_unlock;
  182. }
  183. if (mr->ibmr.pd != qp->ibqp.pd) {
  184. pr_err("Page-fault with different PDs for QP and MR.\n");
  185. ret = -EFAULT;
  186. goto srcu_unlock;
  187. }
  188. current_seq = ACCESS_ONCE(mr->umem->odp_data->notifiers_seq);
  189. /*
  190. * Ensure the sequence number is valid for some time before we call
  191. * gup.
  192. */
  193. smp_rmb();
  194. /*
  195. * Avoid branches - this code will perform correctly
  196. * in all iterations (in iteration 2 and above,
  197. * bytes_committed == 0).
  198. */
  199. io_virt += pfault->mpfault.bytes_committed;
  200. bcnt -= pfault->mpfault.bytes_committed;
  201. start_idx = (io_virt - (mr->mmkey.iova & PAGE_MASK)) >> PAGE_SHIFT;
  202. if (mr->umem->writable)
  203. access_mask |= ODP_WRITE_ALLOWED_BIT;
  204. npages = ib_umem_odp_map_dma_pages(mr->umem, io_virt, bcnt,
  205. access_mask, current_seq);
  206. if (npages < 0) {
  207. ret = npages;
  208. goto srcu_unlock;
  209. }
  210. if (npages > 0) {
  211. mutex_lock(&mr->umem->odp_data->umem_mutex);
  212. if (!ib_umem_mmu_notifier_retry(mr->umem, current_seq)) {
  213. /*
  214. * No need to check whether the MTTs really belong to
  215. * this MR, since ib_umem_odp_map_dma_pages already
  216. * checks this.
  217. */
  218. ret = mlx5_ib_update_mtt(mr, start_idx, npages, 0);
  219. } else {
  220. ret = -EAGAIN;
  221. }
  222. mutex_unlock(&mr->umem->odp_data->umem_mutex);
  223. if (ret < 0) {
  224. if (ret != -EAGAIN)
  225. pr_err("Failed to update mkey page tables\n");
  226. goto srcu_unlock;
  227. }
  228. if (bytes_mapped) {
  229. u32 new_mappings = npages * PAGE_SIZE -
  230. (io_virt - round_down(io_virt, PAGE_SIZE));
  231. *bytes_mapped += min_t(u32, new_mappings, bcnt);
  232. }
  233. }
  234. srcu_unlock:
  235. if (ret == -EAGAIN) {
  236. if (!mr->umem->odp_data->dying) {
  237. struct ib_umem_odp *odp_data = mr->umem->odp_data;
  238. unsigned long timeout =
  239. msecs_to_jiffies(MMU_NOTIFIER_TIMEOUT);
  240. if (!wait_for_completion_timeout(
  241. &odp_data->notifier_completion,
  242. timeout)) {
  243. pr_warn("timeout waiting for mmu notifier completion\n");
  244. }
  245. } else {
  246. /* The MR is being killed, kill the QP as well. */
  247. ret = -EFAULT;
  248. }
  249. }
  250. srcu_read_unlock(&mib_dev->mr_srcu, srcu_key);
  251. pfault->mpfault.bytes_committed = 0;
  252. return ret ? ret : npages;
  253. }
  254. /**
  255. * Parse a series of data segments for page fault handling.
  256. *
  257. * @qp the QP on which the fault occurred.
  258. * @pfault contains page fault information.
  259. * @wqe points at the first data segment in the WQE.
  260. * @wqe_end points after the end of the WQE.
  261. * @bytes_mapped receives the number of bytes that the function was able to
  262. * map. This allows the caller to decide intelligently whether
  263. * enough memory was mapped to resolve the page fault
  264. * successfully (e.g. enough for the next MTU, or the entire
  265. * WQE).
  266. * @total_wqe_bytes receives the total data size of this WQE in bytes (minus
  267. * the committed bytes).
  268. *
  269. * Returns the number of pages loaded if positive, zero for an empty WQE, or a
  270. * negative error code.
  271. */
  272. static int pagefault_data_segments(struct mlx5_ib_qp *qp,
  273. struct mlx5_ib_pfault *pfault, void *wqe,
  274. void *wqe_end, u32 *bytes_mapped,
  275. u32 *total_wqe_bytes, int receive_queue)
  276. {
  277. int ret = 0, npages = 0;
  278. u64 io_virt;
  279. u32 key;
  280. u32 byte_count;
  281. size_t bcnt;
  282. int inline_segment;
  283. /* Skip SRQ next-WQE segment. */
  284. if (receive_queue && qp->ibqp.srq)
  285. wqe += sizeof(struct mlx5_wqe_srq_next_seg);
  286. if (bytes_mapped)
  287. *bytes_mapped = 0;
  288. if (total_wqe_bytes)
  289. *total_wqe_bytes = 0;
  290. while (wqe < wqe_end) {
  291. struct mlx5_wqe_data_seg *dseg = wqe;
  292. io_virt = be64_to_cpu(dseg->addr);
  293. key = be32_to_cpu(dseg->lkey);
  294. byte_count = be32_to_cpu(dseg->byte_count);
  295. inline_segment = !!(byte_count & MLX5_INLINE_SEG);
  296. bcnt = byte_count & ~MLX5_INLINE_SEG;
  297. if (inline_segment) {
  298. bcnt = bcnt & MLX5_WQE_INLINE_SEG_BYTE_COUNT_MASK;
  299. wqe += ALIGN(sizeof(struct mlx5_wqe_inline_seg) + bcnt,
  300. 16);
  301. } else {
  302. wqe += sizeof(*dseg);
  303. }
  304. /* receive WQE end of sg list. */
  305. if (receive_queue && bcnt == 0 && key == MLX5_INVALID_LKEY &&
  306. io_virt == 0)
  307. break;
  308. if (!inline_segment && total_wqe_bytes) {
  309. *total_wqe_bytes += bcnt - min_t(size_t, bcnt,
  310. pfault->mpfault.bytes_committed);
  311. }
  312. /* A zero length data segment designates a length of 2GB. */
  313. if (bcnt == 0)
  314. bcnt = 1U << 31;
  315. if (inline_segment || bcnt <= pfault->mpfault.bytes_committed) {
  316. pfault->mpfault.bytes_committed -=
  317. min_t(size_t, bcnt,
  318. pfault->mpfault.bytes_committed);
  319. continue;
  320. }
  321. ret = pagefault_single_data_segment(qp, pfault, key, io_virt,
  322. bcnt, bytes_mapped);
  323. if (ret < 0)
  324. break;
  325. npages += ret;
  326. }
  327. return ret < 0 ? ret : npages;
  328. }
  329. /*
  330. * Parse initiator WQE. Advances the wqe pointer to point at the
  331. * scatter-gather list, and set wqe_end to the end of the WQE.
  332. */
  333. static int mlx5_ib_mr_initiator_pfault_handler(
  334. struct mlx5_ib_qp *qp, struct mlx5_ib_pfault *pfault,
  335. void **wqe, void **wqe_end, int wqe_length)
  336. {
  337. struct mlx5_ib_dev *dev = to_mdev(qp->ibqp.pd->device);
  338. struct mlx5_wqe_ctrl_seg *ctrl = *wqe;
  339. u16 wqe_index = pfault->mpfault.wqe.wqe_index;
  340. unsigned ds, opcode;
  341. #if defined(DEBUG)
  342. u32 ctrl_wqe_index, ctrl_qpn;
  343. #endif
  344. u32 qpn = qp->trans_qp.base.mqp.qpn;
  345. ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK;
  346. if (ds * MLX5_WQE_DS_UNITS > wqe_length) {
  347. mlx5_ib_err(dev, "Unable to read the complete WQE. ds = 0x%x, ret = 0x%x\n",
  348. ds, wqe_length);
  349. return -EFAULT;
  350. }
  351. if (ds == 0) {
  352. mlx5_ib_err(dev, "Got WQE with zero DS. wqe_index=%x, qpn=%x\n",
  353. wqe_index, qpn);
  354. return -EFAULT;
  355. }
  356. #if defined(DEBUG)
  357. ctrl_wqe_index = (be32_to_cpu(ctrl->opmod_idx_opcode) &
  358. MLX5_WQE_CTRL_WQE_INDEX_MASK) >>
  359. MLX5_WQE_CTRL_WQE_INDEX_SHIFT;
  360. if (wqe_index != ctrl_wqe_index) {
  361. mlx5_ib_err(dev, "Got WQE with invalid wqe_index. wqe_index=0x%x, qpn=0x%x ctrl->wqe_index=0x%x\n",
  362. wqe_index, qpn,
  363. ctrl_wqe_index);
  364. return -EFAULT;
  365. }
  366. ctrl_qpn = (be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_QPN_MASK) >>
  367. MLX5_WQE_CTRL_QPN_SHIFT;
  368. if (qpn != ctrl_qpn) {
  369. mlx5_ib_err(dev, "Got WQE with incorrect QP number. wqe_index=0x%x, qpn=0x%x ctrl->qpn=0x%x\n",
  370. wqe_index, qpn,
  371. ctrl_qpn);
  372. return -EFAULT;
  373. }
  374. #endif /* DEBUG */
  375. *wqe_end = *wqe + ds * MLX5_WQE_DS_UNITS;
  376. *wqe += sizeof(*ctrl);
  377. opcode = be32_to_cpu(ctrl->opmod_idx_opcode) &
  378. MLX5_WQE_CTRL_OPCODE_MASK;
  379. switch (qp->ibqp.qp_type) {
  380. case IB_QPT_RC:
  381. switch (opcode) {
  382. case MLX5_OPCODE_SEND:
  383. case MLX5_OPCODE_SEND_IMM:
  384. case MLX5_OPCODE_SEND_INVAL:
  385. if (!(dev->odp_caps.per_transport_caps.rc_odp_caps &
  386. IB_ODP_SUPPORT_SEND))
  387. goto invalid_transport_or_opcode;
  388. break;
  389. case MLX5_OPCODE_RDMA_WRITE:
  390. case MLX5_OPCODE_RDMA_WRITE_IMM:
  391. if (!(dev->odp_caps.per_transport_caps.rc_odp_caps &
  392. IB_ODP_SUPPORT_WRITE))
  393. goto invalid_transport_or_opcode;
  394. *wqe += sizeof(struct mlx5_wqe_raddr_seg);
  395. break;
  396. case MLX5_OPCODE_RDMA_READ:
  397. if (!(dev->odp_caps.per_transport_caps.rc_odp_caps &
  398. IB_ODP_SUPPORT_READ))
  399. goto invalid_transport_or_opcode;
  400. *wqe += sizeof(struct mlx5_wqe_raddr_seg);
  401. break;
  402. default:
  403. goto invalid_transport_or_opcode;
  404. }
  405. break;
  406. case IB_QPT_UD:
  407. switch (opcode) {
  408. case MLX5_OPCODE_SEND:
  409. case MLX5_OPCODE_SEND_IMM:
  410. if (!(dev->odp_caps.per_transport_caps.ud_odp_caps &
  411. IB_ODP_SUPPORT_SEND))
  412. goto invalid_transport_or_opcode;
  413. *wqe += sizeof(struct mlx5_wqe_datagram_seg);
  414. break;
  415. default:
  416. goto invalid_transport_or_opcode;
  417. }
  418. break;
  419. default:
  420. invalid_transport_or_opcode:
  421. mlx5_ib_err(dev, "ODP fault on QP of an unsupported opcode or transport. transport: 0x%x opcode: 0x%x.\n",
  422. qp->ibqp.qp_type, opcode);
  423. return -EFAULT;
  424. }
  425. return 0;
  426. }
  427. /*
  428. * Parse responder WQE. Advances the wqe pointer to point at the
  429. * scatter-gather list, and set wqe_end to the end of the WQE.
  430. */
  431. static int mlx5_ib_mr_responder_pfault_handler(
  432. struct mlx5_ib_qp *qp, struct mlx5_ib_pfault *pfault,
  433. void **wqe, void **wqe_end, int wqe_length)
  434. {
  435. struct mlx5_ib_dev *dev = to_mdev(qp->ibqp.pd->device);
  436. struct mlx5_ib_wq *wq = &qp->rq;
  437. int wqe_size = 1 << wq->wqe_shift;
  438. if (qp->ibqp.srq) {
  439. mlx5_ib_err(dev, "ODP fault on SRQ is not supported\n");
  440. return -EFAULT;
  441. }
  442. if (qp->wq_sig) {
  443. mlx5_ib_err(dev, "ODP fault with WQE signatures is not supported\n");
  444. return -EFAULT;
  445. }
  446. if (wqe_size > wqe_length) {
  447. mlx5_ib_err(dev, "Couldn't read all of the receive WQE's content\n");
  448. return -EFAULT;
  449. }
  450. switch (qp->ibqp.qp_type) {
  451. case IB_QPT_RC:
  452. if (!(dev->odp_caps.per_transport_caps.rc_odp_caps &
  453. IB_ODP_SUPPORT_RECV))
  454. goto invalid_transport_or_opcode;
  455. break;
  456. default:
  457. invalid_transport_or_opcode:
  458. mlx5_ib_err(dev, "ODP fault on QP of an unsupported transport. transport: 0x%x\n",
  459. qp->ibqp.qp_type);
  460. return -EFAULT;
  461. }
  462. *wqe_end = *wqe + wqe_size;
  463. return 0;
  464. }
  465. static void mlx5_ib_mr_wqe_pfault_handler(struct mlx5_ib_qp *qp,
  466. struct mlx5_ib_pfault *pfault)
  467. {
  468. struct mlx5_ib_dev *dev = to_mdev(qp->ibqp.pd->device);
  469. int ret;
  470. void *wqe, *wqe_end;
  471. u32 bytes_mapped, total_wqe_bytes;
  472. char *buffer = NULL;
  473. int resume_with_error = 0;
  474. u16 wqe_index = pfault->mpfault.wqe.wqe_index;
  475. int requestor = pfault->mpfault.flags & MLX5_PFAULT_REQUESTOR;
  476. u32 qpn = qp->trans_qp.base.mqp.qpn;
  477. buffer = (char *)__get_free_page(GFP_KERNEL);
  478. if (!buffer) {
  479. mlx5_ib_err(dev, "Error allocating memory for IO page fault handling.\n");
  480. resume_with_error = 1;
  481. goto resolve_page_fault;
  482. }
  483. ret = mlx5_ib_read_user_wqe(qp, requestor, wqe_index, buffer,
  484. PAGE_SIZE, &qp->trans_qp.base);
  485. if (ret < 0) {
  486. mlx5_ib_err(dev, "Failed reading a WQE following page fault, error=%x, wqe_index=%x, qpn=%x\n",
  487. -ret, wqe_index, qpn);
  488. resume_with_error = 1;
  489. goto resolve_page_fault;
  490. }
  491. wqe = buffer;
  492. if (requestor)
  493. ret = mlx5_ib_mr_initiator_pfault_handler(qp, pfault, &wqe,
  494. &wqe_end, ret);
  495. else
  496. ret = mlx5_ib_mr_responder_pfault_handler(qp, pfault, &wqe,
  497. &wqe_end, ret);
  498. if (ret < 0) {
  499. resume_with_error = 1;
  500. goto resolve_page_fault;
  501. }
  502. if (wqe >= wqe_end) {
  503. mlx5_ib_err(dev, "ODP fault on invalid WQE.\n");
  504. resume_with_error = 1;
  505. goto resolve_page_fault;
  506. }
  507. ret = pagefault_data_segments(qp, pfault, wqe, wqe_end, &bytes_mapped,
  508. &total_wqe_bytes, !requestor);
  509. if (ret == -EAGAIN) {
  510. goto resolve_page_fault;
  511. } else if (ret < 0 || total_wqe_bytes > bytes_mapped) {
  512. mlx5_ib_err(dev, "Error getting user pages for page fault. Error: 0x%x\n",
  513. -ret);
  514. resume_with_error = 1;
  515. goto resolve_page_fault;
  516. }
  517. resolve_page_fault:
  518. mlx5_ib_page_fault_resume(qp, pfault, resume_with_error);
  519. mlx5_ib_dbg(dev, "PAGE FAULT completed. QP 0x%x resume_with_error=%d, flags: 0x%x\n",
  520. qpn, resume_with_error,
  521. pfault->mpfault.flags);
  522. free_page((unsigned long)buffer);
  523. }
  524. static int pages_in_range(u64 address, u32 length)
  525. {
  526. return (ALIGN(address + length, PAGE_SIZE) -
  527. (address & PAGE_MASK)) >> PAGE_SHIFT;
  528. }
  529. static void mlx5_ib_mr_rdma_pfault_handler(struct mlx5_ib_qp *qp,
  530. struct mlx5_ib_pfault *pfault)
  531. {
  532. struct mlx5_pagefault *mpfault = &pfault->mpfault;
  533. u64 address;
  534. u32 length;
  535. u32 prefetch_len = mpfault->bytes_committed;
  536. int prefetch_activated = 0;
  537. u32 rkey = mpfault->rdma.r_key;
  538. int ret;
  539. /* The RDMA responder handler handles the page fault in two parts.
  540. * First it brings the necessary pages for the current packet
  541. * (and uses the pfault context), and then (after resuming the QP)
  542. * prefetches more pages. The second operation cannot use the pfault
  543. * context and therefore uses the dummy_pfault context allocated on
  544. * the stack */
  545. struct mlx5_ib_pfault dummy_pfault = {};
  546. dummy_pfault.mpfault.bytes_committed = 0;
  547. mpfault->rdma.rdma_va += mpfault->bytes_committed;
  548. mpfault->rdma.rdma_op_len -= min(mpfault->bytes_committed,
  549. mpfault->rdma.rdma_op_len);
  550. mpfault->bytes_committed = 0;
  551. address = mpfault->rdma.rdma_va;
  552. length = mpfault->rdma.rdma_op_len;
  553. /* For some operations, the hardware cannot tell the exact message
  554. * length, and in those cases it reports zero. Use prefetch
  555. * logic. */
  556. if (length == 0) {
  557. prefetch_activated = 1;
  558. length = mpfault->rdma.packet_size;
  559. prefetch_len = min(MAX_PREFETCH_LEN, prefetch_len);
  560. }
  561. ret = pagefault_single_data_segment(qp, pfault, rkey, address, length,
  562. NULL);
  563. if (ret == -EAGAIN) {
  564. /* We're racing with an invalidation, don't prefetch */
  565. prefetch_activated = 0;
  566. } else if (ret < 0 || pages_in_range(address, length) > ret) {
  567. mlx5_ib_page_fault_resume(qp, pfault, 1);
  568. return;
  569. }
  570. mlx5_ib_page_fault_resume(qp, pfault, 0);
  571. /* At this point, there might be a new pagefault already arriving in
  572. * the eq, switch to the dummy pagefault for the rest of the
  573. * processing. We're still OK with the objects being alive as the
  574. * work-queue is being fenced. */
  575. if (prefetch_activated) {
  576. ret = pagefault_single_data_segment(qp, &dummy_pfault, rkey,
  577. address,
  578. prefetch_len,
  579. NULL);
  580. if (ret < 0) {
  581. pr_warn("Prefetch failed (ret = %d, prefetch_activated = %d) for QPN %d, address: 0x%.16llx, length = 0x%.16x\n",
  582. ret, prefetch_activated,
  583. qp->ibqp.qp_num, address, prefetch_len);
  584. }
  585. }
  586. }
  587. void mlx5_ib_mr_pfault_handler(struct mlx5_ib_qp *qp,
  588. struct mlx5_ib_pfault *pfault)
  589. {
  590. u8 event_subtype = pfault->mpfault.event_subtype;
  591. switch (event_subtype) {
  592. case MLX5_PFAULT_SUBTYPE_WQE:
  593. mlx5_ib_mr_wqe_pfault_handler(qp, pfault);
  594. break;
  595. case MLX5_PFAULT_SUBTYPE_RDMA:
  596. mlx5_ib_mr_rdma_pfault_handler(qp, pfault);
  597. break;
  598. default:
  599. pr_warn("Invalid page fault event subtype: 0x%x\n",
  600. event_subtype);
  601. mlx5_ib_page_fault_resume(qp, pfault, 1);
  602. break;
  603. }
  604. }
  605. static void mlx5_ib_qp_pfault_action(struct work_struct *work)
  606. {
  607. struct mlx5_ib_pfault *pfault = container_of(work,
  608. struct mlx5_ib_pfault,
  609. work);
  610. enum mlx5_ib_pagefault_context context =
  611. mlx5_ib_get_pagefault_context(&pfault->mpfault);
  612. struct mlx5_ib_qp *qp = container_of(pfault, struct mlx5_ib_qp,
  613. pagefaults[context]);
  614. mlx5_ib_mr_pfault_handler(qp, pfault);
  615. }
  616. void mlx5_ib_qp_disable_pagefaults(struct mlx5_ib_qp *qp)
  617. {
  618. unsigned long flags;
  619. spin_lock_irqsave(&qp->disable_page_faults_lock, flags);
  620. qp->disable_page_faults = 1;
  621. spin_unlock_irqrestore(&qp->disable_page_faults_lock, flags);
  622. /*
  623. * Note that at this point, we are guarenteed that no more
  624. * work queue elements will be posted to the work queue with
  625. * the QP we are closing.
  626. */
  627. flush_workqueue(mlx5_ib_page_fault_wq);
  628. }
  629. void mlx5_ib_qp_enable_pagefaults(struct mlx5_ib_qp *qp)
  630. {
  631. unsigned long flags;
  632. spin_lock_irqsave(&qp->disable_page_faults_lock, flags);
  633. qp->disable_page_faults = 0;
  634. spin_unlock_irqrestore(&qp->disable_page_faults_lock, flags);
  635. }
  636. static void mlx5_ib_pfault_handler(struct mlx5_core_qp *qp,
  637. struct mlx5_pagefault *pfault)
  638. {
  639. /*
  640. * Note that we will only get one fault event per QP per context
  641. * (responder/initiator, read/write), until we resolve the page fault
  642. * with the mlx5_ib_page_fault_resume command. Since this function is
  643. * called from within the work element, there is no risk of missing
  644. * events.
  645. */
  646. struct mlx5_ib_qp *mibqp = to_mibqp(qp);
  647. enum mlx5_ib_pagefault_context context =
  648. mlx5_ib_get_pagefault_context(pfault);
  649. struct mlx5_ib_pfault *qp_pfault = &mibqp->pagefaults[context];
  650. qp_pfault->mpfault = *pfault;
  651. /* No need to stop interrupts here since we are in an interrupt */
  652. spin_lock(&mibqp->disable_page_faults_lock);
  653. if (!mibqp->disable_page_faults)
  654. queue_work(mlx5_ib_page_fault_wq, &qp_pfault->work);
  655. spin_unlock(&mibqp->disable_page_faults_lock);
  656. }
  657. void mlx5_ib_odp_create_qp(struct mlx5_ib_qp *qp)
  658. {
  659. int i;
  660. qp->disable_page_faults = 1;
  661. spin_lock_init(&qp->disable_page_faults_lock);
  662. qp->trans_qp.base.mqp.pfault_handler = mlx5_ib_pfault_handler;
  663. for (i = 0; i < MLX5_IB_PAGEFAULT_CONTEXTS; ++i)
  664. INIT_WORK(&qp->pagefaults[i].work, mlx5_ib_qp_pfault_action);
  665. }
  666. int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev)
  667. {
  668. int ret;
  669. ret = init_srcu_struct(&ibdev->mr_srcu);
  670. if (ret)
  671. return ret;
  672. return 0;
  673. }
  674. void mlx5_ib_odp_remove_one(struct mlx5_ib_dev *ibdev)
  675. {
  676. cleanup_srcu_struct(&ibdev->mr_srcu);
  677. }
  678. int __init mlx5_ib_odp_init(void)
  679. {
  680. mlx5_ib_page_fault_wq = alloc_ordered_workqueue("mlx5_ib_page_faults",
  681. WQ_MEM_RECLAIM);
  682. if (!mlx5_ib_page_fault_wq)
  683. return -ENOMEM;
  684. return 0;
  685. }
  686. void mlx5_ib_odp_cleanup(void)
  687. {
  688. destroy_workqueue(mlx5_ib_page_fault_wq);
  689. }