gpio-altera.c 10 KB

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  1. /*
  2. * Copyright (C) 2013 Altera Corporation
  3. * Based on gpio-mpc8xxx.c
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License as published by
  7. * the Free Software Foundation; either version 2 of the License, or
  8. * (at your option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program. If not, see <http://www.gnu.org/licenses/>.
  17. */
  18. #include <linux/io.h>
  19. #include <linux/module.h>
  20. #include <linux/of_gpio.h>
  21. #include <linux/platform_device.h>
  22. #define ALTERA_GPIO_MAX_NGPIO 32
  23. #define ALTERA_GPIO_DATA 0x0
  24. #define ALTERA_GPIO_DIR 0x4
  25. #define ALTERA_GPIO_IRQ_MASK 0x8
  26. #define ALTERA_GPIO_EDGE_CAP 0xc
  27. /**
  28. * struct altera_gpio_chip
  29. * @mmchip : memory mapped chip structure.
  30. * @gpio_lock : synchronization lock so that new irq/set/get requests
  31. will be blocked until the current one completes.
  32. * @interrupt_trigger : specifies the hardware configured IRQ trigger type
  33. (rising, falling, both, high)
  34. * @mapped_irq : kernel mapped irq number.
  35. */
  36. struct altera_gpio_chip {
  37. struct of_mm_gpio_chip mmchip;
  38. spinlock_t gpio_lock;
  39. int interrupt_trigger;
  40. int mapped_irq;
  41. };
  42. static void altera_gpio_irq_unmask(struct irq_data *d)
  43. {
  44. struct altera_gpio_chip *altera_gc;
  45. struct of_mm_gpio_chip *mm_gc;
  46. unsigned long flags;
  47. u32 intmask;
  48. altera_gc = gpiochip_get_data(irq_data_get_irq_chip_data(d));
  49. mm_gc = &altera_gc->mmchip;
  50. spin_lock_irqsave(&altera_gc->gpio_lock, flags);
  51. intmask = readl(mm_gc->regs + ALTERA_GPIO_IRQ_MASK);
  52. /* Set ALTERA_GPIO_IRQ_MASK bit to unmask */
  53. intmask |= BIT(irqd_to_hwirq(d));
  54. writel(intmask, mm_gc->regs + ALTERA_GPIO_IRQ_MASK);
  55. spin_unlock_irqrestore(&altera_gc->gpio_lock, flags);
  56. }
  57. static void altera_gpio_irq_mask(struct irq_data *d)
  58. {
  59. struct altera_gpio_chip *altera_gc;
  60. struct of_mm_gpio_chip *mm_gc;
  61. unsigned long flags;
  62. u32 intmask;
  63. altera_gc = gpiochip_get_data(irq_data_get_irq_chip_data(d));
  64. mm_gc = &altera_gc->mmchip;
  65. spin_lock_irqsave(&altera_gc->gpio_lock, flags);
  66. intmask = readl(mm_gc->regs + ALTERA_GPIO_IRQ_MASK);
  67. /* Clear ALTERA_GPIO_IRQ_MASK bit to mask */
  68. intmask &= ~BIT(irqd_to_hwirq(d));
  69. writel(intmask, mm_gc->regs + ALTERA_GPIO_IRQ_MASK);
  70. spin_unlock_irqrestore(&altera_gc->gpio_lock, flags);
  71. }
  72. /**
  73. * This controller's IRQ type is synthesized in hardware, so this function
  74. * just checks if the requested set_type matches the synthesized IRQ type
  75. */
  76. static int altera_gpio_irq_set_type(struct irq_data *d,
  77. unsigned int type)
  78. {
  79. struct altera_gpio_chip *altera_gc;
  80. altera_gc = gpiochip_get_data(irq_data_get_irq_chip_data(d));
  81. if (type == IRQ_TYPE_NONE)
  82. return 0;
  83. if (type == IRQ_TYPE_LEVEL_HIGH &&
  84. altera_gc->interrupt_trigger == IRQ_TYPE_LEVEL_HIGH)
  85. return 0;
  86. if (type == IRQ_TYPE_EDGE_RISING &&
  87. altera_gc->interrupt_trigger == IRQ_TYPE_EDGE_RISING)
  88. return 0;
  89. if (type == IRQ_TYPE_EDGE_FALLING &&
  90. altera_gc->interrupt_trigger == IRQ_TYPE_EDGE_FALLING)
  91. return 0;
  92. if (type == IRQ_TYPE_EDGE_BOTH &&
  93. altera_gc->interrupt_trigger == IRQ_TYPE_EDGE_BOTH)
  94. return 0;
  95. return -EINVAL;
  96. }
  97. static unsigned int altera_gpio_irq_startup(struct irq_data *d)
  98. {
  99. altera_gpio_irq_unmask(d);
  100. return 0;
  101. }
  102. static struct irq_chip altera_irq_chip = {
  103. .name = "altera-gpio",
  104. .irq_mask = altera_gpio_irq_mask,
  105. .irq_unmask = altera_gpio_irq_unmask,
  106. .irq_set_type = altera_gpio_irq_set_type,
  107. .irq_startup = altera_gpio_irq_startup,
  108. .irq_shutdown = altera_gpio_irq_mask,
  109. };
  110. static int altera_gpio_get(struct gpio_chip *gc, unsigned offset)
  111. {
  112. struct of_mm_gpio_chip *mm_gc;
  113. mm_gc = to_of_mm_gpio_chip(gc);
  114. return !!(readl(mm_gc->regs + ALTERA_GPIO_DATA) & BIT(offset));
  115. }
  116. static void altera_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
  117. {
  118. struct of_mm_gpio_chip *mm_gc;
  119. struct altera_gpio_chip *chip;
  120. unsigned long flags;
  121. unsigned int data_reg;
  122. mm_gc = to_of_mm_gpio_chip(gc);
  123. chip = gpiochip_get_data(gc);
  124. spin_lock_irqsave(&chip->gpio_lock, flags);
  125. data_reg = readl(mm_gc->regs + ALTERA_GPIO_DATA);
  126. if (value)
  127. data_reg |= BIT(offset);
  128. else
  129. data_reg &= ~BIT(offset);
  130. writel(data_reg, mm_gc->regs + ALTERA_GPIO_DATA);
  131. spin_unlock_irqrestore(&chip->gpio_lock, flags);
  132. }
  133. static int altera_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
  134. {
  135. struct of_mm_gpio_chip *mm_gc;
  136. struct altera_gpio_chip *chip;
  137. unsigned long flags;
  138. unsigned int gpio_ddr;
  139. mm_gc = to_of_mm_gpio_chip(gc);
  140. chip = gpiochip_get_data(gc);
  141. spin_lock_irqsave(&chip->gpio_lock, flags);
  142. /* Set pin as input, assumes software controlled IP */
  143. gpio_ddr = readl(mm_gc->regs + ALTERA_GPIO_DIR);
  144. gpio_ddr &= ~BIT(offset);
  145. writel(gpio_ddr, mm_gc->regs + ALTERA_GPIO_DIR);
  146. spin_unlock_irqrestore(&chip->gpio_lock, flags);
  147. return 0;
  148. }
  149. static int altera_gpio_direction_output(struct gpio_chip *gc,
  150. unsigned offset, int value)
  151. {
  152. struct of_mm_gpio_chip *mm_gc;
  153. struct altera_gpio_chip *chip;
  154. unsigned long flags;
  155. unsigned int data_reg, gpio_ddr;
  156. mm_gc = to_of_mm_gpio_chip(gc);
  157. chip = gpiochip_get_data(gc);
  158. spin_lock_irqsave(&chip->gpio_lock, flags);
  159. /* Sets the GPIO value */
  160. data_reg = readl(mm_gc->regs + ALTERA_GPIO_DATA);
  161. if (value)
  162. data_reg |= BIT(offset);
  163. else
  164. data_reg &= ~BIT(offset);
  165. writel(data_reg, mm_gc->regs + ALTERA_GPIO_DATA);
  166. /* Set pin as output, assumes software controlled IP */
  167. gpio_ddr = readl(mm_gc->regs + ALTERA_GPIO_DIR);
  168. gpio_ddr |= BIT(offset);
  169. writel(gpio_ddr, mm_gc->regs + ALTERA_GPIO_DIR);
  170. spin_unlock_irqrestore(&chip->gpio_lock, flags);
  171. return 0;
  172. }
  173. static void altera_gpio_irq_edge_handler(struct irq_desc *desc)
  174. {
  175. struct altera_gpio_chip *altera_gc;
  176. struct irq_chip *chip;
  177. struct of_mm_gpio_chip *mm_gc;
  178. struct irq_domain *irqdomain;
  179. unsigned long status;
  180. int i;
  181. altera_gc = gpiochip_get_data(irq_desc_get_handler_data(desc));
  182. chip = irq_desc_get_chip(desc);
  183. mm_gc = &altera_gc->mmchip;
  184. irqdomain = altera_gc->mmchip.gc.irqdomain;
  185. chained_irq_enter(chip, desc);
  186. while ((status =
  187. (readl(mm_gc->regs + ALTERA_GPIO_EDGE_CAP) &
  188. readl(mm_gc->regs + ALTERA_GPIO_IRQ_MASK)))) {
  189. writel(status, mm_gc->regs + ALTERA_GPIO_EDGE_CAP);
  190. for_each_set_bit(i, &status, mm_gc->gc.ngpio) {
  191. generic_handle_irq(irq_find_mapping(irqdomain, i));
  192. }
  193. }
  194. chained_irq_exit(chip, desc);
  195. }
  196. static void altera_gpio_irq_leveL_high_handler(struct irq_desc *desc)
  197. {
  198. struct altera_gpio_chip *altera_gc;
  199. struct irq_chip *chip;
  200. struct of_mm_gpio_chip *mm_gc;
  201. struct irq_domain *irqdomain;
  202. unsigned long status;
  203. int i;
  204. altera_gc = gpiochip_get_data(irq_desc_get_handler_data(desc));
  205. chip = irq_desc_get_chip(desc);
  206. mm_gc = &altera_gc->mmchip;
  207. irqdomain = altera_gc->mmchip.gc.irqdomain;
  208. chained_irq_enter(chip, desc);
  209. status = readl(mm_gc->regs + ALTERA_GPIO_DATA);
  210. status &= readl(mm_gc->regs + ALTERA_GPIO_IRQ_MASK);
  211. for_each_set_bit(i, &status, mm_gc->gc.ngpio) {
  212. generic_handle_irq(irq_find_mapping(irqdomain, i));
  213. }
  214. chained_irq_exit(chip, desc);
  215. }
  216. static int altera_gpio_probe(struct platform_device *pdev)
  217. {
  218. struct device_node *node = pdev->dev.of_node;
  219. int reg, ret;
  220. struct altera_gpio_chip *altera_gc;
  221. altera_gc = devm_kzalloc(&pdev->dev, sizeof(*altera_gc), GFP_KERNEL);
  222. if (!altera_gc)
  223. return -ENOMEM;
  224. spin_lock_init(&altera_gc->gpio_lock);
  225. if (of_property_read_u32(node, "altr,ngpio", &reg))
  226. /* By default assume maximum ngpio */
  227. altera_gc->mmchip.gc.ngpio = ALTERA_GPIO_MAX_NGPIO;
  228. else
  229. altera_gc->mmchip.gc.ngpio = reg;
  230. if (altera_gc->mmchip.gc.ngpio > ALTERA_GPIO_MAX_NGPIO) {
  231. dev_warn(&pdev->dev,
  232. "ngpio is greater than %d, defaulting to %d\n",
  233. ALTERA_GPIO_MAX_NGPIO, ALTERA_GPIO_MAX_NGPIO);
  234. altera_gc->mmchip.gc.ngpio = ALTERA_GPIO_MAX_NGPIO;
  235. }
  236. altera_gc->mmchip.gc.direction_input = altera_gpio_direction_input;
  237. altera_gc->mmchip.gc.direction_output = altera_gpio_direction_output;
  238. altera_gc->mmchip.gc.get = altera_gpio_get;
  239. altera_gc->mmchip.gc.set = altera_gpio_set;
  240. altera_gc->mmchip.gc.owner = THIS_MODULE;
  241. altera_gc->mmchip.gc.parent = &pdev->dev;
  242. ret = of_mm_gpiochip_add_data(node, &altera_gc->mmchip, altera_gc);
  243. if (ret) {
  244. dev_err(&pdev->dev, "Failed adding memory mapped gpiochip\n");
  245. return ret;
  246. }
  247. platform_set_drvdata(pdev, altera_gc);
  248. altera_gc->mapped_irq = platform_get_irq(pdev, 0);
  249. if (altera_gc->mapped_irq < 0)
  250. goto skip_irq;
  251. if (of_property_read_u32(node, "altr,interrupt-type", &reg)) {
  252. ret = -EINVAL;
  253. dev_err(&pdev->dev,
  254. "altr,interrupt-type value not set in device tree\n");
  255. goto teardown;
  256. }
  257. altera_gc->interrupt_trigger = reg;
  258. ret = gpiochip_irqchip_add(&altera_gc->mmchip.gc, &altera_irq_chip, 0,
  259. handle_simple_irq, IRQ_TYPE_NONE);
  260. if (ret) {
  261. dev_err(&pdev->dev, "could not add irqchip\n");
  262. goto teardown;
  263. }
  264. gpiochip_set_chained_irqchip(&altera_gc->mmchip.gc,
  265. &altera_irq_chip,
  266. altera_gc->mapped_irq,
  267. altera_gc->interrupt_trigger == IRQ_TYPE_LEVEL_HIGH ?
  268. altera_gpio_irq_leveL_high_handler :
  269. altera_gpio_irq_edge_handler);
  270. skip_irq:
  271. return 0;
  272. teardown:
  273. of_mm_gpiochip_remove(&altera_gc->mmchip);
  274. pr_err("%s: registration failed with status %d\n",
  275. node->full_name, ret);
  276. return ret;
  277. }
  278. static int altera_gpio_remove(struct platform_device *pdev)
  279. {
  280. struct altera_gpio_chip *altera_gc = platform_get_drvdata(pdev);
  281. of_mm_gpiochip_remove(&altera_gc->mmchip);
  282. return 0;
  283. }
  284. static const struct of_device_id altera_gpio_of_match[] = {
  285. { .compatible = "altr,pio-1.0", },
  286. {},
  287. };
  288. MODULE_DEVICE_TABLE(of, altera_gpio_of_match);
  289. static struct platform_driver altera_gpio_driver = {
  290. .driver = {
  291. .name = "altera_gpio",
  292. .of_match_table = of_match_ptr(altera_gpio_of_match),
  293. },
  294. .probe = altera_gpio_probe,
  295. .remove = altera_gpio_remove,
  296. };
  297. static int __init altera_gpio_init(void)
  298. {
  299. return platform_driver_register(&altera_gpio_driver);
  300. }
  301. subsys_initcall(altera_gpio_init);
  302. static void __exit altera_gpio_exit(void)
  303. {
  304. platform_driver_unregister(&altera_gpio_driver);
  305. }
  306. module_exit(altera_gpio_exit);
  307. MODULE_AUTHOR("Tien Hock Loh <thloh@altera.com>");
  308. MODULE_DESCRIPTION("Altera GPIO driver");
  309. MODULE_LICENSE("GPL");