ti-pci.txt 3.8 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697
  1. TI PCI Controllers
  2. PCIe Designware Controller
  3. - compatible: Should be "ti,dra7-pcie" for RC (deprecated)
  4. Should be "ti,dra7-pcie-ep" for EP (deprecated)
  5. Should be "ti,dra746-pcie-rc" for dra74x/dra76 in RC mode
  6. Should be "ti,dra746-pcie-ep" for dra74x/dra76 in EP mode
  7. Should be "ti,dra726-pcie-rc" for dra72x in RC mode
  8. Should be "ti,dra726-pcie-ep" for dra72x in EP mode
  9. - phys : list of PHY specifiers (used by generic PHY framework)
  10. - phy-names : must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
  11. number of PHYs as specified in *phys* property.
  12. - ti,hwmods : Name of the hwmod associated to the pcie, "pcie<X>",
  13. where <X> is the instance number of the pcie from the HW spec.
  14. - num-lanes as specified in ../designware-pcie.txt
  15. - syscon-lane-conf : phandle/offset pair. Phandle to the system control module and the
  16. register offset to specify 1 lane or 2 lane.
  17. - syscon-lane-sel : phandle/offset pair. Phandle to the system control module and the
  18. register offset to specify lane selection.
  19. HOST MODE
  20. =========
  21. - reg : Two register ranges as listed in the reg-names property
  22. - reg-names : The first entry must be "ti-conf" for the TI specific registers
  23. The second entry must be "rc-dbics" for the designware pcie
  24. registers
  25. The third entry must be "config" for the PCIe configuration space
  26. - interrupts : Two interrupt entries must be specified. The first one is for
  27. main interrupt line and the second for MSI interrupt line.
  28. - #address-cells,
  29. #size-cells,
  30. #interrupt-cells,
  31. device_type,
  32. ranges,
  33. interrupt-map-mask,
  34. interrupt-map : as specified in ../designware-pcie.txt
  35. DEVICE MODE
  36. ===========
  37. - reg : Four register ranges as listed in the reg-names property
  38. - reg-names : "ti-conf" for the TI specific registers
  39. "ep_dbics" for the standard configuration registers as
  40. they are locally accessed within the DIF CS space
  41. "ep_dbics2" for the standard configuration registers as
  42. they are locally accessed within the DIF CS2 space
  43. "addr_space" used to map remote RC address space
  44. - interrupts : one interrupt entries must be specified for main interrupt.
  45. - num-ib-windows : number of inbound address translation windows
  46. - num-ob-windows : number of outbound address translation windows
  47. - syscon-legacy-mode: phandle to the syscon dt node. The 1st argument should
  48. contain the register offset within syscon and the 2nd
  49. argument should contain the bit field for setting the
  50. legacy mode
  51. Optional Property:
  52. - gpios : Should be added if a gpio line is required to drive PERST# line
  53. NOTE: Two dt nodes should be added for each PCI controller; one for host
  54. mode and another for device mode. So in order for PCI to
  55. work in host mode, EP mode dt node should be disabled and in order to PCI to
  56. work in EP mode, host mode dt node should be disabled. And host mode and EP
  57. mode are mutually exclusive.
  58. Example:
  59. axi {
  60. compatible = "simple-bus";
  61. #size-cells = <1>;
  62. #address-cells = <1>;
  63. ranges = <0x51000000 0x51000000 0x3000
  64. 0x0 0x20000000 0x10000000>;
  65. pcie@51000000 {
  66. compatible = "ti,dra7-pcie";
  67. reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>;
  68. reg-names = "rc_dbics", "ti_conf", "config";
  69. interrupts = <0 232 0x4>, <0 233 0x4>;
  70. #address-cells = <3>;
  71. #size-cells = <2>;
  72. device_type = "pci";
  73. ranges = <0x81000000 0 0 0x03000 0 0x00010000
  74. 0x82000000 0 0x20013000 0x13000 0 0xffed000>;
  75. #interrupt-cells = <1>;
  76. num-lanes = <1>;
  77. ti,hwmods = "pcie1";
  78. phys = <&pcie1_phy>;
  79. phy-names = "pcie-phy0";
  80. interrupt-map-mask = <0 0 0 7>;
  81. interrupt-map = <0 0 0 1 &pcie_intc 1>,
  82. <0 0 0 2 &pcie_intc 2>,
  83. <0 0 0 3 &pcie_intc 3>,
  84. <0 0 0 4 &pcie_intc 4>;
  85. pcie_intc: interrupt-controller {
  86. interrupt-controller;
  87. #address-cells = <0>;
  88. #interrupt-cells = <1>;
  89. };
  90. };
  91. };