mcftimer.h 2.3 KB

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  1. /****************************************************************************/
  2. /*
  3. * mcftimer.h -- ColdFire internal TIMER support defines.
  4. *
  5. * (C) Copyright 1999-2006, Greg Ungerer <gerg@snapgear.com>
  6. * (C) Copyright 2000, Lineo Inc. (www.lineo.com)
  7. */
  8. /****************************************************************************/
  9. #ifndef mcftimer_h
  10. #define mcftimer_h
  11. /****************************************************************************/
  12. /*
  13. * Define the TIMER register set addresses.
  14. */
  15. #define MCFTIMER_TMR 0x00 /* Timer Mode reg (r/w) */
  16. #define MCFTIMER_TRR 0x04 /* Timer Reference (r/w) */
  17. #define MCFTIMER_TCR 0x08 /* Timer Capture reg (r/w) */
  18. #define MCFTIMER_TCN 0x0C /* Timer Counter reg (r/w) */
  19. #if defined(CONFIG_M53xx) || defined(CONFIG_M5441x)
  20. #define MCFTIMER_TER 0x03 /* Timer Event reg (r/w) */
  21. #else
  22. #define MCFTIMER_TER 0x11 /* Timer Event reg (r/w) */
  23. #endif
  24. /*
  25. * Bit definitions for the Timer Mode Register (TMR).
  26. * Register bit flags are common across ColdFires.
  27. */
  28. #define MCFTIMER_TMR_PREMASK 0xff00 /* Prescalar mask */
  29. #define MCFTIMER_TMR_DISCE 0x0000 /* Disable capture */
  30. #define MCFTIMER_TMR_ANYCE 0x00c0 /* Capture any edge */
  31. #define MCFTIMER_TMR_FALLCE 0x0080 /* Capture fallingedge */
  32. #define MCFTIMER_TMR_RISECE 0x0040 /* Capture rising edge */
  33. #define MCFTIMER_TMR_ENOM 0x0020 /* Enable output toggle */
  34. #define MCFTIMER_TMR_DISOM 0x0000 /* Do single output pulse */
  35. #define MCFTIMER_TMR_ENORI 0x0010 /* Enable ref interrupt */
  36. #define MCFTIMER_TMR_DISORI 0x0000 /* Disable ref interrupt */
  37. #define MCFTIMER_TMR_RESTART 0x0008 /* Restart counter */
  38. #define MCFTIMER_TMR_FREERUN 0x0000 /* Free running counter */
  39. #define MCFTIMER_TMR_CLKTIN 0x0006 /* Input clock is TIN */
  40. #define MCFTIMER_TMR_CLK16 0x0004 /* Input clock is /16 */
  41. #define MCFTIMER_TMR_CLK1 0x0002 /* Input clock is /1 */
  42. #define MCFTIMER_TMR_CLKSTOP 0x0000 /* Stop counter */
  43. #define MCFTIMER_TMR_ENABLE 0x0001 /* Enable timer */
  44. #define MCFTIMER_TMR_DISABLE 0x0000 /* Disable timer */
  45. /*
  46. * Bit definitions for the Timer Event Registers (TER).
  47. */
  48. #define MCFTIMER_TER_CAP 0x01 /* Capture event */
  49. #define MCFTIMER_TER_REF 0x02 /* Reference event */
  50. /****************************************************************************/
  51. #endif /* mcftimer_h */