/******************************************************************** * Copyright (C) 2013-2014 Texas Instruments Incorporated. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * */ #ifndef CSLR_SCP_H_ #define CSLR_SCP_H_ #ifdef __cplusplus extern "C" { #endif #include #include /************************************************************************** * Register Overlay Structure for __ALL__ **************************************************************************/ typedef struct { volatile Uint32 INPUT_ENS_REG1; volatile Uint32 INPUT_ENS_REG2; volatile Uint32 LDO_CTRL_REG; volatile Uint32 FUNC_CONFIG_REG; volatile Uint32 DRIVER_DATA_CONFIG1; volatile Uint32 DRIVER_DATA_CONFIG2; volatile Uint32 BGTRIM_REG; volatile Uint32 RTRIM_REG; volatile Uint32 ANA_OBSERVE_REG1; volatile Uint32 TRIM_OBSERVE_REG; volatile Uint32 IO_OVERRIDE_REG; volatile Uint32 TEST_CONFIG_REG; volatile Uint32 PATTGEN_PRELOAD; volatile Uint32 DFT_OBSERVE_REG1; } CSL_ScpRegs; /************************************************************************** * Register Macros **************************************************************************/ /* Enable controls for different analog and digital circuits in the IP. */ #define CSL_SCP_INPUT_ENS_REG1 (0x0U) /* Enable controls for different analog and digital circuits in the IP. */ #define CSL_SCP_INPUT_ENS_REG2 (0x4U) /* LDO control registers - details of the controlling parameter - TBD. */ #define CSL_SCP_LDO_CTRL_REG (0x8U) /* Functional Configuration registers */ #define CSL_SCP_FUNC_CONFIG_REG (0xCU) /* Configures the Driver data pattern -details TBD */ #define CSL_SCP_DRIVER_DATA_CONFIG1 (0x10U) /* Configures the Driver data pattern -details TBD */ #define CSL_SCP_DRIVER_DATA_CONFIG2 (0x14U) /* The IP requires some values to be remembered in EFUSE. This register * provides an alternative to EFUSE. */ #define CSL_SCP_BGTRIM_REG (0x18U) /* The IP requires some values to be remembered in EFUSE. This register * provides an alternative to EFUSE. */ #define CSL_SCP_RTRIM_REG (0x1CU) /* Observes the status of Analog */ #define CSL_SCP_ANA_OBSERVE_REG1 (0x20U) /* Observes the status of Analog */ #define CSL_SCP_TRIM_OBSERVE_REG (0x24U) /* Override the Input and outputs of the IP through these reg controls */ #define CSL_SCP_IO_OVERRIDE_REG (0x28U) /* Test related configuration registers */ #define CSL_SCP_TEST_CONFIG_REG (0x2CU) /* Pattern generator (31 bit) LFSR Seed or preload value */ #define CSL_SCP_PATTGEN_PRELOAD (0x30U) /* Observe register to read the internal status of the enables after the scp * overrides.Also to improve testability of the override logic. */ #define CSL_SCP_DFT_OBSERVE_REG1 (0x34U) /************************************************************************** * Field Definition Macros **************************************************************************/ /* INPUT_ENS_REG1 */ #define CSL_SCP_INPUT_ENS_REG1_MEM_EN_TX_MASK (0x80000000U) #define CSL_SCP_INPUT_ENS_REG1_MEM_EN_TX_SHIFT (31U) #define CSL_SCP_INPUT_ENS_REG1_MEM_EN_TX_RESETVAL (0x00000000U) #define CSL_SCP_INPUT_ENS_REG1_MEM_EN_TX_MAX (0x00000001U) #define CSL_SCP_INPUT_ENS_REG1_MEM_OVRD_EN_TX_MASK (0x40000000U) #define CSL_SCP_INPUT_ENS_REG1_MEM_OVRD_EN_TX_SHIFT (30U) #define CSL_SCP_INPUT_ENS_REG1_MEM_OVRD_EN_TX_RESETVAL (0x00000000U) #define CSL_SCP_INPUT_ENS_REG1_MEM_OVRD_EN_TX_MAX (0x00000001U) #define CSL_SCP_INPUT_ENS_REG1_MEM_EN_BG_MASK (0x20000000U) #define CSL_SCP_INPUT_ENS_REG1_MEM_EN_BG_SHIFT (29U) #define CSL_SCP_INPUT_ENS_REG1_MEM_EN_BG_RESETVAL (0x00000000U) #define CSL_SCP_INPUT_ENS_REG1_MEM_EN_BG_MAX (0x00000001U) #define CSL_SCP_INPUT_ENS_REG1_MEM_OVRD_EN_BG_MASK (0x10000000U) #define CSL_SCP_INPUT_ENS_REG1_MEM_OVRD_EN_BG_SHIFT (28U) #define CSL_SCP_INPUT_ENS_REG1_MEM_OVRD_EN_BG_RESETVAL (0x00000000U) #define CSL_SCP_INPUT_ENS_REG1_MEM_OVRD_EN_BG_MAX (0x00000001U) #define CSL_SCP_INPUT_ENS_REG1_MEM_EN_TXALDO_MASK (0x08000000U) #define CSL_SCP_INPUT_ENS_REG1_MEM_EN_TXALDO_SHIFT (27U) #define CSL_SCP_INPUT_ENS_REG1_MEM_EN_TXALDO_RESETVAL (0x00000000U) #define CSL_SCP_INPUT_ENS_REG1_MEM_EN_TXALDO_MAX (0x00000001U) #define CSL_SCP_INPUT_ENS_REG1_MEM_OVRD_EN_TXALDO_MASK (0x04000000U) #define CSL_SCP_INPUT_ENS_REG1_MEM_OVRD_EN_TXALDO_SHIFT (26U) #define CSL_SCP_INPUT_ENS_REG1_MEM_OVRD_EN_TXALDO_RESETVAL (0x00000000U) #define CSL_SCP_INPUT_ENS_REG1_MEM_OVRD_EN_TXALDO_MAX (0x00000001U) #define CSL_SCP_INPUT_ENS_REG1_MEM_EN_TXDLDO_MASK (0x02000000U) #define CSL_SCP_INPUT_ENS_REG1_MEM_EN_TXDLDO_SHIFT (25U) #define CSL_SCP_INPUT_ENS_REG1_MEM_EN_TXDLDO_RESETVAL (0x00000000U) #define CSL_SCP_INPUT_ENS_REG1_MEM_EN_TXDLDO_MAX (0x00000001U) #define CSL_SCP_INPUT_ENS_REG1_MEM_OVRD_EN_TXDLDO_MASK (0x01000000U) #define CSL_SCP_INPUT_ENS_REG1_MEM_OVRD_EN_TXDLDO_SHIFT (24U) #define CSL_SCP_INPUT_ENS_REG1_MEM_OVRD_EN_TXDLDO_RESETVAL (0x00000000U) #define CSL_SCP_INPUT_ENS_REG1_MEM_OVRD_EN_TXDLDO_MAX (0x00000001U) #define CSL_SCP_INPUT_ENS_REG1_MEM_ISO_LDODOMAIN_MASK (0x00800000U) #define CSL_SCP_INPUT_ENS_REG1_MEM_ISO_LDODOMAIN_SHIFT (23U) #define CSL_SCP_INPUT_ENS_REG1_MEM_ISO_LDODOMAIN_RESETVAL (0x00000000U) #define CSL_SCP_INPUT_ENS_REG1_MEM_ISO_LDODOMAIN_MAX (0x00000001U) #define CSL_SCP_INPUT_ENS_REG1_MEM_OVRD_ISO_LDODOMAIN_MASK (0x00400000U) #define CSL_SCP_INPUT_ENS_REG1_MEM_OVRD_ISO_LDODOMAIN_SHIFT (22U) #define CSL_SCP_INPUT_ENS_REG1_MEM_OVRD_ISO_LDODOMAIN_RESETVAL (0x00000000U) #define CSL_SCP_INPUT_ENS_REG1_MEM_OVRD_ISO_LDODOMAIN_MAX (0x00000001U) #define CSL_SCP_INPUT_ENS_REG1_MEM_RSTN_LDODOMAIN_MASK (0x00200000U) #define CSL_SCP_INPUT_ENS_REG1_MEM_RSTN_LDODOMAIN_SHIFT (21U) #define CSL_SCP_INPUT_ENS_REG1_MEM_RSTN_LDODOMAIN_RESETVAL (0x00000000U) #define CSL_SCP_INPUT_ENS_REG1_MEM_RSTN_LDODOMAIN_MAX (0x00000001U) #define CSL_SCP_INPUT_ENS_REG1_MEM_OVRD_RSTN_LDODOMAIN_MASK (0x00100000U) #define CSL_SCP_INPUT_ENS_REG1_MEM_OVRD_RSTN_LDODOMAIN_SHIFT (20U) #define CSL_SCP_INPUT_ENS_REG1_MEM_OVRD_RSTN_LDODOMAIN_RESETVAL (0x00000000U) #define CSL_SCP_INPUT_ENS_REG1_MEM_OVRD_RSTN_LDODOMAIN_MAX (0x00000001U) #define CSL_SCP_INPUT_ENS_REG1_MEM_EN_RX_DETECT_MASK (0x000C0000U) #define CSL_SCP_INPUT_ENS_REG1_MEM_EN_RX_DETECT_SHIFT (18U) #define CSL_SCP_INPUT_ENS_REG1_MEM_EN_RX_DETECT_RESETVAL (0x00000000U) #define CSL_SCP_INPUT_ENS_REG1_MEM_EN_RX_DETECT_MAX (0x00000003U) #define CSL_SCP_INPUT_ENS_REG1_MEM_OVRD_EN_RX_DETECT_MASK (0x00020000U) #define CSL_SCP_INPUT_ENS_REG1_MEM_OVRD_EN_RX_DETECT_SHIFT (17U) #define CSL_SCP_INPUT_ENS_REG1_MEM_OVRD_EN_RX_DETECT_RESETVAL (0x00000000U) #define CSL_SCP_INPUT_ENS_REG1_MEM_OVRD_EN_RX_DETECT_MAX (0x00000001U) #define CSL_SCP_INPUT_ENS_REG1_MEM_EN_LFPS_MASK (0x00010000U) #define CSL_SCP_INPUT_ENS_REG1_MEM_EN_LFPS_SHIFT (16U) #define CSL_SCP_INPUT_ENS_REG1_MEM_EN_LFPS_RESETVAL (0x00000000U) #define CSL_SCP_INPUT_ENS_REG1_MEM_EN_LFPS_MAX (0x00000001U) #define CSL_SCP_INPUT_ENS_REG1_MEM_OVRD_EN_LFPS_MASK (0x00008000U) #define CSL_SCP_INPUT_ENS_REG1_MEM_OVRD_EN_LFPS_SHIFT (15U) #define CSL_SCP_INPUT_ENS_REG1_MEM_OVRD_EN_LFPS_RESETVAL (0x00000000U) #define CSL_SCP_INPUT_ENS_REG1_MEM_OVRD_EN_LFPS_MAX (0x00000001U) #define CSL_SCP_INPUT_ENS_REG1_MEM_EN_IDLE_MASK (0x00004000U) #define CSL_SCP_INPUT_ENS_REG1_MEM_EN_IDLE_SHIFT (14U) #define CSL_SCP_INPUT_ENS_REG1_MEM_EN_IDLE_RESETVAL (0x00000000U) #define CSL_SCP_INPUT_ENS_REG1_MEM_EN_IDLE_MAX (0x00000001U) #define CSL_SCP_INPUT_ENS_REG1_MEM_OVRD_EN_IDLE_MASK (0x00002000U) #define CSL_SCP_INPUT_ENS_REG1_MEM_OVRD_EN_IDLE_SHIFT (13U) #define CSL_SCP_INPUT_ENS_REG1_MEM_OVRD_EN_IDLE_RESETVAL (0x00000000U) #define CSL_SCP_INPUT_ENS_REG1_MEM_OVRD_EN_IDLE_MAX (0x00000001U) #define CSL_SCP_INPUT_ENS_REG1_MEM_HS_RATE_MASK (0x00001800U) #define CSL_SCP_INPUT_ENS_REG1_MEM_HS_RATE_SHIFT (11U) #define CSL_SCP_INPUT_ENS_REG1_MEM_HS_RATE_RESETVAL (0x00000000U) #define CSL_SCP_INPUT_ENS_REG1_MEM_HS_RATE_MAX (0x00000003U) #define CSL_SCP_INPUT_ENS_REG1_MEM_OVRD_HS_RATE_MASK (0x00000400U) #define CSL_SCP_INPUT_ENS_REG1_MEM_OVRD_HS_RATE_SHIFT (10U) #define CSL_SCP_INPUT_ENS_REG1_MEM_OVRD_HS_RATE_RESETVAL (0x00000000U) #define CSL_SCP_INPUT_ENS_REG1_MEM_OVRD_HS_RATE_MAX (0x00000001U) #define CSL_SCP_INPUT_ENS_REG1_MEM_SWING_MASK (0x000003C0U) #define CSL_SCP_INPUT_ENS_REG1_MEM_SWING_SHIFT (6U) #define CSL_SCP_INPUT_ENS_REG1_MEM_SWING_RESETVAL (0x00000000U) #define CSL_SCP_INPUT_ENS_REG1_MEM_SWING_MAX (0x0000000fU) #define CSL_SCP_INPUT_ENS_REG1_MEM_OVRD_SWING_MASK (0x00000020U) #define CSL_SCP_INPUT_ENS_REG1_MEM_OVRD_SWING_SHIFT (5U) #define CSL_SCP_INPUT_ENS_REG1_MEM_OVRD_SWING_RESETVAL (0x00000000U) #define CSL_SCP_INPUT_ENS_REG1_MEM_OVRD_SWING_MAX (0x00000001U) #define CSL_SCP_INPUT_ENS_REG1_MEM_STD_MASK (0x0000001CU) #define CSL_SCP_INPUT_ENS_REG1_MEM_STD_SHIFT (2U) #define CSL_SCP_INPUT_ENS_REG1_MEM_STD_RESETVAL (0x00000000U) #define CSL_SCP_INPUT_ENS_REG1_MEM_STD_MAX (0x00000007U) #define CSL_SCP_INPUT_ENS_REG1_MEM_OVRD_STD_MASK (0x00000002U) #define CSL_SCP_INPUT_ENS_REG1_MEM_OVRD_STD_SHIFT (1U) #define CSL_SCP_INPUT_ENS_REG1_MEM_OVRD_STD_RESETVAL (0x00000000U) #define CSL_SCP_INPUT_ENS_REG1_MEM_OVRD_STD_MAX (0x00000001U) #define CSL_SCP_INPUT_ENS_REG1_MEM_SPAREBITS_SHANTANUTX_INPUT_ENS_REG1_MASK (0x00000001U) #define CSL_SCP_INPUT_ENS_REG1_MEM_SPAREBITS_SHANTANUTX_INPUT_ENS_REG1_SHIFT (0U) #define CSL_SCP_INPUT_ENS_REG1_MEM_SPAREBITS_SHANTANUTX_INPUT_ENS_REG1_RESETVAL (0x00000000U) #define CSL_SCP_INPUT_ENS_REG1_MEM_SPAREBITS_SHANTANUTX_INPUT_ENS_REG1_MAX (0x00000001U) #define CSL_SCP_INPUT_ENS_REG1_RESETVAL (0x00000000U) /* INPUT_ENS_REG2 */ #define CSL_SCP_INPUT_ENS_REG2_MEM_MPHY_TRAN_CTRL_MASK (0xF0000000U) #define CSL_SCP_INPUT_ENS_REG2_MEM_MPHY_TRAN_CTRL_SHIFT (28U) #define CSL_SCP_INPUT_ENS_REG2_MEM_MPHY_TRAN_CTRL_RESETVAL (0x00000000U) #define CSL_SCP_INPUT_ENS_REG2_MEM_MPHY_TRAN_CTRL_MAX (0x0000000fU) #define CSL_SCP_INPUT_ENS_REG2_MEM_OVRD_MPHY_TRAN_CTRL_MASK (0x08000000U) #define CSL_SCP_INPUT_ENS_REG2_MEM_OVRD_MPHY_TRAN_CTRL_SHIFT (27U) #define CSL_SCP_INPUT_ENS_REG2_MEM_OVRD_MPHY_TRAN_CTRL_RESETVAL (0x00000000U) #define CSL_SCP_INPUT_ENS_REG2_MEM_OVRD_MPHY_TRAN_CTRL_MAX (0x00000001U) #define CSL_SCP_INPUT_ENS_REG2_MEM_MPHY_CONFIG_MASK (0x06000000U) #define CSL_SCP_INPUT_ENS_REG2_MEM_MPHY_CONFIG_SHIFT (25U) #define CSL_SCP_INPUT_ENS_REG2_MEM_MPHY_CONFIG_RESETVAL (0x00000000U) #define CSL_SCP_INPUT_ENS_REG2_MEM_MPHY_CONFIG_MAX (0x00000003U) #define CSL_SCP_INPUT_ENS_REG2_MEM_OVRD_MPHY_CONFIG_MASK (0x01000000U) #define CSL_SCP_INPUT_ENS_REG2_MEM_OVRD_MPHY_CONFIG_SHIFT (24U) #define CSL_SCP_INPUT_ENS_REG2_MEM_OVRD_MPHY_CONFIG_RESETVAL (0x00000000U) #define CSL_SCP_INPUT_ENS_REG2_MEM_OVRD_MPHY_CONFIG_MAX (0x00000001U) #define CSL_SCP_INPUT_ENS_REG2_MEM_EN_TXREG_MASK (0x00800000U) #define CSL_SCP_INPUT_ENS_REG2_MEM_EN_TXREG_SHIFT (23U) #define CSL_SCP_INPUT_ENS_REG2_MEM_EN_TXREG_RESETVAL (0x00000000U) #define CSL_SCP_INPUT_ENS_REG2_MEM_EN_TXREG_MAX (0x00000001U) #define CSL_SCP_INPUT_ENS_REG2_MEM_OVRD_EN_TXREG_MASK (0x00400000U) #define CSL_SCP_INPUT_ENS_REG2_MEM_OVRD_EN_TXREG_SHIFT (22U) #define CSL_SCP_INPUT_ENS_REG2_MEM_OVRD_EN_TXREG_RESETVAL (0x00000000U) #define CSL_SCP_INPUT_ENS_REG2_MEM_OVRD_EN_TXREG_MAX (0x00000001U) #define CSL_SCP_INPUT_ENS_REG2_MEM_EN_LOWSWING_MASK (0x00200000U) #define CSL_SCP_INPUT_ENS_REG2_MEM_EN_LOWSWING_SHIFT (21U) #define CSL_SCP_INPUT_ENS_REG2_MEM_EN_LOWSWING_RESETVAL (0x00000000U) #define CSL_SCP_INPUT_ENS_REG2_MEM_EN_LOWSWING_MAX (0x00000001U) #define CSL_SCP_INPUT_ENS_REG2_MEM_OVRD_EN_LOWSWING_MASK (0x00100000U) #define CSL_SCP_INPUT_ENS_REG2_MEM_OVRD_EN_LOWSWING_SHIFT (20U) #define CSL_SCP_INPUT_ENS_REG2_MEM_OVRD_EN_LOWSWING_RESETVAL (0x00000000U) #define CSL_SCP_INPUT_ENS_REG2_MEM_OVRD_EN_LOWSWING_MAX (0x00000001U) #define CSL_SCP_INPUT_ENS_REG2_MEM_EN_SYNC_PULSE_MASK (0x00080000U) #define CSL_SCP_INPUT_ENS_REG2_MEM_EN_SYNC_PULSE_SHIFT (19U) #define CSL_SCP_INPUT_ENS_REG2_MEM_EN_SYNC_PULSE_RESETVAL (0x00000000U) #define CSL_SCP_INPUT_ENS_REG2_MEM_EN_SYNC_PULSE_MAX (0x00000001U) #define CSL_SCP_INPUT_ENS_REG2_MEM_OVRD_EN_SYNC_PULSE_MASK (0x00040000U) #define CSL_SCP_INPUT_ENS_REG2_MEM_OVRD_EN_SYNC_PULSE_SHIFT (18U) #define CSL_SCP_INPUT_ENS_REG2_MEM_OVRD_EN_SYNC_PULSE_RESETVAL (0x00000000U) #define CSL_SCP_INPUT_ENS_REG2_MEM_OVRD_EN_SYNC_PULSE_MAX (0x00000001U) #define CSL_SCP_INPUT_ENS_REG2_MEM_TXREG_CTRL_MASK (0x0003FFFCU) #define CSL_SCP_INPUT_ENS_REG2_MEM_TXREG_CTRL_SHIFT (2U) #define CSL_SCP_INPUT_ENS_REG2_MEM_TXREG_CTRL_RESETVAL (0x00000000U) #define CSL_SCP_INPUT_ENS_REG2_MEM_TXREG_CTRL_MAX (0x0000ffffU) #define CSL_SCP_INPUT_ENS_REG2_MEM_SPAREBITS_SHANTANUTX_INPUT_ENS_REG2_MASK (0x00000003U) #define CSL_SCP_INPUT_ENS_REG2_MEM_SPAREBITS_SHANTANUTX_INPUT_ENS_REG2_SHIFT (0U) #define CSL_SCP_INPUT_ENS_REG2_MEM_SPAREBITS_SHANTANUTX_INPUT_ENS_REG2_RESETVAL (0x00000000U) #define CSL_SCP_INPUT_ENS_REG2_MEM_SPAREBITS_SHANTANUTX_INPUT_ENS_REG2_MAX (0x00000003U) #define CSL_SCP_INPUT_ENS_REG2_RESETVAL (0x00000000U) /* LDO_CTRL_REG */ #define CSL_SCP_LDO_CTRL_REG_MEM_TXALDO_CTRL_MASK (0xFFFF0000U) #define CSL_SCP_LDO_CTRL_REG_MEM_TXALDO_CTRL_SHIFT (16U) #define CSL_SCP_LDO_CTRL_REG_MEM_TXALDO_CTRL_RESETVAL (0x00000006U) #define CSL_SCP_LDO_CTRL_REG_MEM_TXALDO_CTRL_MAX (0x0000ffffU) #define CSL_SCP_LDO_CTRL_REG_MEM_TXDLDO_CTRL_MASK (0x0000FFFFU) #define CSL_SCP_LDO_CTRL_REG_MEM_TXDLDO_CTRL_SHIFT (0U) #define CSL_SCP_LDO_CTRL_REG_MEM_TXDLDO_CTRL_RESETVAL (0x0000000aU) #define CSL_SCP_LDO_CTRL_REG_MEM_TXDLDO_CTRL_MAX (0x0000ffffU) #define CSL_SCP_LDO_CTRL_REG_RESETVAL (0x0006000aU) /* FUNC_CONFIG_REG */ #define CSL_SCP_FUNC_CONFIG_REG_MEM_INVPAIR_MASK (0x80000000U) #define CSL_SCP_FUNC_CONFIG_REG_MEM_INVPAIR_SHIFT (31U) #define CSL_SCP_FUNC_CONFIG_REG_MEM_INVPAIR_RESETVAL (0x00000000U) #define CSL_SCP_FUNC_CONFIG_REG_MEM_INVPAIR_MAX (0x00000001U) #define CSL_SCP_FUNC_CONFIG_REG_MEM_DE_MASK (0x7C000000U) #define CSL_SCP_FUNC_CONFIG_REG_MEM_DE_SHIFT (26U) #define CSL_SCP_FUNC_CONFIG_REG_MEM_DE_RESETVAL (0x00000000U) #define CSL_SCP_FUNC_CONFIG_REG_MEM_DE_MAX (0x0000001fU) #define CSL_SCP_FUNC_CONFIG_REG_MEM_OVRD_DE_MASK (0x02000000U) #define CSL_SCP_FUNC_CONFIG_REG_MEM_OVRD_DE_SHIFT (25U) #define CSL_SCP_FUNC_CONFIG_REG_MEM_OVRD_DE_RESETVAL (0x00000000U) #define CSL_SCP_FUNC_CONFIG_REG_MEM_OVRD_DE_MAX (0x00000001U) #define CSL_SCP_FUNC_CONFIG_REG_MEM_EN_EXT_VREF_MASK (0x01000000U) #define CSL_SCP_FUNC_CONFIG_REG_MEM_EN_EXT_VREF_SHIFT (24U) #define CSL_SCP_FUNC_CONFIG_REG_MEM_EN_EXT_VREF_RESETVAL (0x00000000U) #define CSL_SCP_FUNC_CONFIG_REG_MEM_EN_EXT_VREF_MAX (0x00000001U) #define CSL_SCP_FUNC_CONFIG_REG_MEM_EN_DCC_MASK (0x00C00000U) #define CSL_SCP_FUNC_CONFIG_REG_MEM_EN_DCC_SHIFT (22U) #define CSL_SCP_FUNC_CONFIG_REG_MEM_EN_DCC_RESETVAL (0x00000000U) #define CSL_SCP_FUNC_CONFIG_REG_MEM_EN_DCC_MAX (0x00000003U) #define CSL_SCP_FUNC_CONFIG_REG_MEM_EN8_MASK (0x00200000U) #define CSL_SCP_FUNC_CONFIG_REG_MEM_EN8_SHIFT (21U) #define CSL_SCP_FUNC_CONFIG_REG_MEM_EN8_RESETVAL (0x00000000U) #define CSL_SCP_FUNC_CONFIG_REG_MEM_EN8_MAX (0x00000001U) #define CSL_SCP_FUNC_CONFIG_REG_MEM_EDGE_BOOST_MASK (0x001E0000U) #define CSL_SCP_FUNC_CONFIG_REG_MEM_EDGE_BOOST_SHIFT (17U) #define CSL_SCP_FUNC_CONFIG_REG_MEM_EDGE_BOOST_RESETVAL (0x00000000U) #define CSL_SCP_FUNC_CONFIG_REG_MEM_EDGE_BOOST_MAX (0x0000000fU) #define CSL_SCP_FUNC_CONFIG_REG_MEM_EN_TXA_MASK (0x00010000U) #define CSL_SCP_FUNC_CONFIG_REG_MEM_EN_TXA_SHIFT (16U) #define CSL_SCP_FUNC_CONFIG_REG_MEM_EN_TXA_RESETVAL (0x00000000U) #define CSL_SCP_FUNC_CONFIG_REG_MEM_EN_TXA_MAX (0x00000001U) #define CSL_SCP_FUNC_CONFIG_REG_MEM_OVRD_EN_TXA_MASK (0x00008000U) #define CSL_SCP_FUNC_CONFIG_REG_MEM_OVRD_EN_TXA_SHIFT (15U) #define CSL_SCP_FUNC_CONFIG_REG_MEM_OVRD_EN_TXA_RESETVAL (0x00000000U) #define CSL_SCP_FUNC_CONFIG_REG_MEM_OVRD_EN_TXA_MAX (0x00000001U) #define CSL_SCP_FUNC_CONFIG_REG_MEM_PHOLDL_MASK (0x00004000U) #define CSL_SCP_FUNC_CONFIG_REG_MEM_PHOLDL_SHIFT (14U) #define CSL_SCP_FUNC_CONFIG_REG_MEM_PHOLDL_RESETVAL (0x00000000U) #define CSL_SCP_FUNC_CONFIG_REG_MEM_PHOLDL_MAX (0x00000001U) #define CSL_SCP_FUNC_CONFIG_REG_MEM_OVRD_PHOLDL_MASK (0x00002000U) #define CSL_SCP_FUNC_CONFIG_REG_MEM_OVRD_PHOLDL_SHIFT (13U) #define CSL_SCP_FUNC_CONFIG_REG_MEM_OVRD_PHOLDL_RESETVAL (0x00000000U) #define CSL_SCP_FUNC_CONFIG_REG_MEM_OVRD_PHOLDL_MAX (0x00000001U) #define CSL_SCP_FUNC_CONFIG_REG_MEM_SPAREBITS_SHANTANUTX_FUNC_CONFIG_REG_MASK (0x00001800U) #define CSL_SCP_FUNC_CONFIG_REG_MEM_SPAREBITS_SHANTANUTX_FUNC_CONFIG_REG_SHIFT (11U) #define CSL_SCP_FUNC_CONFIG_REG_MEM_SPAREBITS_SHANTANUTX_FUNC_CONFIG_REG_RESETVAL (0x00000000U) #define CSL_SCP_FUNC_CONFIG_REG_MEM_SPAREBITS_SHANTANUTX_FUNC_CONFIG_REG_MAX (0x00000003U) #define CSL_SCP_FUNC_CONFIG_REG_MEM_EN_TXBCLK_GATING_MASK (0x00000400U) #define CSL_SCP_FUNC_CONFIG_REG_MEM_EN_TXBCLK_GATING_SHIFT (10U) #define CSL_SCP_FUNC_CONFIG_REG_MEM_EN_TXBCLK_GATING_RESETVAL (0x00000001U) #define CSL_SCP_FUNC_CONFIG_REG_MEM_EN_TXBCLK_GATING_MAX (0x00000001U) #define CSL_SCP_FUNC_CONFIG_REG_MEM_COUNT_LIMIT_MASK (0x000003FFU) #define CSL_SCP_FUNC_CONFIG_REG_MEM_COUNT_LIMIT_SHIFT (0U) #define CSL_SCP_FUNC_CONFIG_REG_MEM_COUNT_LIMIT_RESETVAL (0x0000007dU) #define CSL_SCP_FUNC_CONFIG_REG_MEM_COUNT_LIMIT_MAX (0x000003ffU) #define CSL_SCP_FUNC_CONFIG_REG_RESETVAL (0x0000047dU) /* DRIVER_DATA_CONFIG1 */ #define CSL_SCP_DRIVER_DATA_CONFIG1_MEM_EVEN_OUT_CONFIG0_MASK (0xFE000000U) #define CSL_SCP_DRIVER_DATA_CONFIG1_MEM_EVEN_OUT_CONFIG0_SHIFT (25U) #define CSL_SCP_DRIVER_DATA_CONFIG1_MEM_EVEN_OUT_CONFIG0_RESETVAL (0x00000000U) #define CSL_SCP_DRIVER_DATA_CONFIG1_MEM_EVEN_OUT_CONFIG0_MAX (0x0000007fU) #define CSL_SCP_DRIVER_DATA_CONFIG1_MEM_ODD_OUT_CONFIG0_MASK (0x01FC0000U) #define CSL_SCP_DRIVER_DATA_CONFIG1_MEM_ODD_OUT_CONFIG0_SHIFT (18U) #define CSL_SCP_DRIVER_DATA_CONFIG1_MEM_ODD_OUT_CONFIG0_RESETVAL (0x00000000U) #define CSL_SCP_DRIVER_DATA_CONFIG1_MEM_ODD_OUT_CONFIG0_MAX (0x0000007fU) #define CSL_SCP_DRIVER_DATA_CONFIG1_MEM_EVEN_OUT_CONFIG1_MASK (0x0003F800U) #define CSL_SCP_DRIVER_DATA_CONFIG1_MEM_EVEN_OUT_CONFIG1_SHIFT (11U) #define CSL_SCP_DRIVER_DATA_CONFIG1_MEM_EVEN_OUT_CONFIG1_RESETVAL (0x00000000U) #define CSL_SCP_DRIVER_DATA_CONFIG1_MEM_EVEN_OUT_CONFIG1_MAX (0x0000007fU) #define CSL_SCP_DRIVER_DATA_CONFIG1_MEM_ODD_OUT_CONFIG1_MASK (0x000007F0U) #define CSL_SCP_DRIVER_DATA_CONFIG1_MEM_ODD_OUT_CONFIG1_SHIFT (4U) #define CSL_SCP_DRIVER_DATA_CONFIG1_MEM_ODD_OUT_CONFIG1_RESETVAL (0x00000000U) #define CSL_SCP_DRIVER_DATA_CONFIG1_MEM_ODD_OUT_CONFIG1_MAX (0x0000007fU) #define CSL_SCP_DRIVER_DATA_CONFIG1_MEM_SPAREBITS_SHANTANUTX_DRIVER_DATA_CONFIG1_MASK (0x00000001U) #define CSL_SCP_DRIVER_DATA_CONFIG1_MEM_SPAREBITS_SHANTANUTX_DRIVER_DATA_CONFIG1_SHIFT (0U) #define CSL_SCP_DRIVER_DATA_CONFIG1_MEM_SPAREBITS_SHANTANUTX_DRIVER_DATA_CONFIG1_RESETVAL (0x00000000U) #define CSL_SCP_DRIVER_DATA_CONFIG1_MEM_SPAREBITS_SHANTANUTX_DRIVER_DATA_CONFIG1_MAX (0x00000001U) #define CSL_SCP_DRIVER_DATA_CONFIG1_MEM_OVRD_HS_RATE_ANA_OVERRIDE_MASK (0x00000002U) #define CSL_SCP_DRIVER_DATA_CONFIG1_MEM_OVRD_HS_RATE_ANA_OVERRIDE_SHIFT (1U) #define CSL_SCP_DRIVER_DATA_CONFIG1_MEM_OVRD_HS_RATE_ANA_OVERRIDE_RESETVAL (0x00000000U) #define CSL_SCP_DRIVER_DATA_CONFIG1_MEM_OVRD_HS_RATE_ANA_OVERRIDE_MAX (0x00000001U) #define CSL_SCP_DRIVER_DATA_CONFIG1_MEM_HS_RATE_ANA_OVERRIDE_MASK (0x0000000CU) #define CSL_SCP_DRIVER_DATA_CONFIG1_MEM_HS_RATE_ANA_OVERRIDE_SHIFT (2U) #define CSL_SCP_DRIVER_DATA_CONFIG1_MEM_HS_RATE_ANA_OVERRIDE_RESETVAL (0x00000000U) #define CSL_SCP_DRIVER_DATA_CONFIG1_MEM_HS_RATE_ANA_OVERRIDE_MAX (0x00000003U) #define CSL_SCP_DRIVER_DATA_CONFIG1_RESETVAL (0x00000000U) /* DRIVER_DATA_CONFIG2 */ #define CSL_SCP_DRIVER_DATA_CONFIG2_MEM_EVEN_OUT_CONFIG2_MASK (0xFE000000U) #define CSL_SCP_DRIVER_DATA_CONFIG2_MEM_EVEN_OUT_CONFIG2_SHIFT (25U) #define CSL_SCP_DRIVER_DATA_CONFIG2_MEM_EVEN_OUT_CONFIG2_RESETVAL (0x00000000U) #define CSL_SCP_DRIVER_DATA_CONFIG2_MEM_EVEN_OUT_CONFIG2_MAX (0x0000007fU) #define CSL_SCP_DRIVER_DATA_CONFIG2_MEM_ODD_OUT_CONFIG2_MASK (0x01FC0000U) #define CSL_SCP_DRIVER_DATA_CONFIG2_MEM_ODD_OUT_CONFIG2_SHIFT (18U) #define CSL_SCP_DRIVER_DATA_CONFIG2_MEM_ODD_OUT_CONFIG2_RESETVAL (0x00000000U) #define CSL_SCP_DRIVER_DATA_CONFIG2_MEM_ODD_OUT_CONFIG2_MAX (0x0000007fU) #define CSL_SCP_DRIVER_DATA_CONFIG2_MEM_SEL_EVEN_OUT_CONFIG_MASK (0x0003F800U) #define CSL_SCP_DRIVER_DATA_CONFIG2_MEM_SEL_EVEN_OUT_CONFIG_SHIFT (11U) #define CSL_SCP_DRIVER_DATA_CONFIG2_MEM_SEL_EVEN_OUT_CONFIG_RESETVAL (0x00000000U) #define CSL_SCP_DRIVER_DATA_CONFIG2_MEM_SEL_EVEN_OUT_CONFIG_MAX (0x0000007fU) #define CSL_SCP_DRIVER_DATA_CONFIG2_MEM_SEL_ODD_OUT_CONFIG_MASK (0x000007F0U) #define CSL_SCP_DRIVER_DATA_CONFIG2_MEM_SEL_ODD_OUT_CONFIG_SHIFT (4U) #define CSL_SCP_DRIVER_DATA_CONFIG2_MEM_SEL_ODD_OUT_CONFIG_RESETVAL (0x00000000U) #define CSL_SCP_DRIVER_DATA_CONFIG2_MEM_SEL_ODD_OUT_CONFIG_MAX (0x0000007fU) #define CSL_SCP_DRIVER_DATA_CONFIG2_MEM_SPAREBITS_SHANTANUTX_DRIVER_DATA_CONFIG2_MASK (0x0000000FU) #define CSL_SCP_DRIVER_DATA_CONFIG2_MEM_SPAREBITS_SHANTANUTX_DRIVER_DATA_CONFIG2_SHIFT (0U) #define CSL_SCP_DRIVER_DATA_CONFIG2_MEM_SPAREBITS_SHANTANUTX_DRIVER_DATA_CONFIG2_RESETVAL (0x00000000U) #define CSL_SCP_DRIVER_DATA_CONFIG2_MEM_SPAREBITS_SHANTANUTX_DRIVER_DATA_CONFIG2_MAX (0x0000000fU) #define CSL_SCP_DRIVER_DATA_CONFIG2_RESETVAL (0x00000000U) /* BGTRIM_REG */ #define CSL_SCP_BGTRIM_REG_MEM_BGTRIM_MASK (0xFFFF0000U) #define CSL_SCP_BGTRIM_REG_MEM_BGTRIM_SHIFT (16U) #define CSL_SCP_BGTRIM_REG_MEM_BGTRIM_RESETVAL (0x00000000U) #define CSL_SCP_BGTRIM_REG_MEM_BGTRIM_MAX (0x0000ffffU) #define CSL_SCP_BGTRIM_REG_MEM_OVRD_EFUSE_BGTRIM_MASK (0x00008000U) #define CSL_SCP_BGTRIM_REG_MEM_OVRD_EFUSE_BGTRIM_SHIFT (15U) #define CSL_SCP_BGTRIM_REG_MEM_OVRD_EFUSE_BGTRIM_RESETVAL (0x00000000U) #define CSL_SCP_BGTRIM_REG_MEM_OVRD_EFUSE_BGTRIM_MAX (0x00000001U) #define CSL_SCP_BGTRIM_REG_MEM_SPAREBITS_SHANTANUTX_BGTRIM_REG_MASK (0x00007FFFU) #define CSL_SCP_BGTRIM_REG_MEM_SPAREBITS_SHANTANUTX_BGTRIM_REG_SHIFT (0U) #define CSL_SCP_BGTRIM_REG_MEM_SPAREBITS_SHANTANUTX_BGTRIM_REG_RESETVAL (0x00000000U) #define CSL_SCP_BGTRIM_REG_MEM_SPAREBITS_SHANTANUTX_BGTRIM_REG_MAX (0x00007fffU) #define CSL_SCP_BGTRIM_REG_RESETVAL (0x00000000U) /* RTRIM_REG */ #define CSL_SCP_RTRIM_REG_MEM_RTRIM_MASK (0xF8000000U) #define CSL_SCP_RTRIM_REG_MEM_RTRIM_SHIFT (27U) #define CSL_SCP_RTRIM_REG_MEM_RTRIM_RESETVAL (0x00000000U) #define CSL_SCP_RTRIM_REG_MEM_RTRIM_MAX (0x0000001fU) #define CSL_SCP_RTRIM_REG_MEM_OVRD_EFUSE_RTRIM_MASK (0x04000000U) #define CSL_SCP_RTRIM_REG_MEM_OVRD_EFUSE_RTRIM_SHIFT (26U) #define CSL_SCP_RTRIM_REG_MEM_OVRD_EFUSE_RTRIM_RESETVAL (0x00000000U) #define CSL_SCP_RTRIM_REG_MEM_OVRD_EFUSE_RTRIM_MAX (0x00000001U) #define CSL_SCP_RTRIM_REG_MEM_SPAREBITS_SHANTANUTX_RTRIM_REG_MASK (0x03FFFFFFU) #define CSL_SCP_RTRIM_REG_MEM_SPAREBITS_SHANTANUTX_RTRIM_REG_SHIFT (0U) #define CSL_SCP_RTRIM_REG_MEM_SPAREBITS_SHANTANUTX_RTRIM_REG_RESETVAL (0x00000000U) #define CSL_SCP_RTRIM_REG_MEM_SPAREBITS_SHANTANUTX_RTRIM_REG_MAX (0x03ffffffU) #define CSL_SCP_RTRIM_REG_RESETVAL (0x00000000U) /* ANA_OBSERVE_REG1 */ #define CSL_SCP_ANA_OBSERVE_REG1_TXALDO_STS_MASK (0xE0000000U) #define CSL_SCP_ANA_OBSERVE_REG1_TXALDO_STS_SHIFT (29U) #define CSL_SCP_ANA_OBSERVE_REG1_TXALDO_STS_RESETVAL (0x00000000U) #define CSL_SCP_ANA_OBSERVE_REG1_TXALDO_STS_MAX (0x00000007U) #define CSL_SCP_ANA_OBSERVE_REG1_TXALDO_STBL_OUT_MASK (0x10000000U) #define CSL_SCP_ANA_OBSERVE_REG1_TXALDO_STBL_OUT_SHIFT (28U) #define CSL_SCP_ANA_OBSERVE_REG1_TXALDO_STBL_OUT_RESETVAL (0x00000000U) #define CSL_SCP_ANA_OBSERVE_REG1_TXALDO_STBL_OUT_MAX (0x00000001U) #define CSL_SCP_ANA_OBSERVE_REG1_TXDLDO_STS_MASK (0x0E000000U) #define CSL_SCP_ANA_OBSERVE_REG1_TXDLDO_STS_SHIFT (25U) #define CSL_SCP_ANA_OBSERVE_REG1_TXDLDO_STS_RESETVAL (0x00000000U) #define CSL_SCP_ANA_OBSERVE_REG1_TXDLDO_STS_MAX (0x00000007U) #define CSL_SCP_ANA_OBSERVE_REG1_TXDLDO_STBL_OUT_MASK (0x01000000U) #define CSL_SCP_ANA_OBSERVE_REG1_TXDLDO_STBL_OUT_SHIFT (24U) #define CSL_SCP_ANA_OBSERVE_REG1_TXDLDO_STBL_OUT_RESETVAL (0x00000000U) #define CSL_SCP_ANA_OBSERVE_REG1_TXDLDO_STBL_OUT_MAX (0x00000001U) #define CSL_SCP_ANA_OBSERVE_REG1_RX_DET_OUT_MASK (0x00800000U) #define CSL_SCP_ANA_OBSERVE_REG1_RX_DET_OUT_SHIFT (23U) #define CSL_SCP_ANA_OBSERVE_REG1_RX_DET_OUT_RESETVAL (0x00000000U) #define CSL_SCP_ANA_OBSERVE_REG1_RX_DET_OUT_MAX (0x00000001U) #define CSL_SCP_ANA_OBSERVE_REG1_MPHY_CONFIG_RD_MASK (0x00600000U) #define CSL_SCP_ANA_OBSERVE_REG1_MPHY_CONFIG_RD_SHIFT (21U) #define CSL_SCP_ANA_OBSERVE_REG1_MPHY_CONFIG_RD_RESETVAL (0x00000000U) #define CSL_SCP_ANA_OBSERVE_REG1_MPHY_CONFIG_RD_MAX (0x00000003U) #define CSL_SCP_ANA_OBSERVE_REG1_MPHY_TRAN_CTRL_RD_MASK (0x001E0000U) #define CSL_SCP_ANA_OBSERVE_REG1_MPHY_TRAN_CTRL_RD_SHIFT (17U) #define CSL_SCP_ANA_OBSERVE_REG1_MPHY_TRAN_CTRL_RD_RESETVAL (0x00000000U) #define CSL_SCP_ANA_OBSERVE_REG1_MPHY_TRAN_CTRL_RD_MAX (0x0000000fU) #define CSL_SCP_ANA_OBSERVE_REG1_HALF_RATE_EN_RD_MASK (0x00010000U) #define CSL_SCP_ANA_OBSERVE_REG1_HALF_RATE_EN_RD_SHIFT (16U) #define CSL_SCP_ANA_OBSERVE_REG1_HALF_RATE_EN_RD_RESETVAL (0x00000000U) #define CSL_SCP_ANA_OBSERVE_REG1_HALF_RATE_EN_RD_MAX (0x00000001U) #define CSL_SCP_ANA_OBSERVE_REG1_DEEMP_RD_MASK (0x0000C000U) #define CSL_SCP_ANA_OBSERVE_REG1_DEEMP_RD_SHIFT (14U) #define CSL_SCP_ANA_OBSERVE_REG1_DEEMP_RD_RESETVAL (0x00000000U) #define CSL_SCP_ANA_OBSERVE_REG1_DEEMP_RD_MAX (0x00000003U) #define CSL_SCP_ANA_OBSERVE_REG1_LFPS_DATA_RD_MASK (0x00002000U) #define CSL_SCP_ANA_OBSERVE_REG1_LFPS_DATA_RD_SHIFT (13U) #define CSL_SCP_ANA_OBSERVE_REG1_LFPS_DATA_RD_RESETVAL (0x00000000U) #define CSL_SCP_ANA_OBSERVE_REG1_LFPS_DATA_RD_MAX (0x00000001U) #define CSL_SCP_ANA_OBSERVE_REG1_SPAREBITS_SHANTANUTX_ANA_OBSERVE_REG1_MASK (0x00001FFFU) #define CSL_SCP_ANA_OBSERVE_REG1_SPAREBITS_SHANTANUTX_ANA_OBSERVE_REG1_SHIFT (0U) #define CSL_SCP_ANA_OBSERVE_REG1_SPAREBITS_SHANTANUTX_ANA_OBSERVE_REG1_RESETVAL (0x00000000U) #define CSL_SCP_ANA_OBSERVE_REG1_SPAREBITS_SHANTANUTX_ANA_OBSERVE_REG1_MAX (0x00001fffU) #define CSL_SCP_ANA_OBSERVE_REG1_RESETVAL (0x00000000U) /* TRIM_OBSERVE_REG */ #define CSL_SCP_TRIM_OBSERVE_REG_BGTRIM_EFUSE_MASK (0xFFFF0000U) #define CSL_SCP_TRIM_OBSERVE_REG_BGTRIM_EFUSE_SHIFT (16U) #define CSL_SCP_TRIM_OBSERVE_REG_BGTRIM_EFUSE_RESETVAL (0x00000000U) #define CSL_SCP_TRIM_OBSERVE_REG_BGTRIM_EFUSE_MAX (0x0000ffffU) #define CSL_SCP_TRIM_OBSERVE_REG_RTRIM_EFUSE_MASK (0x0000F800U) #define CSL_SCP_TRIM_OBSERVE_REG_RTRIM_EFUSE_SHIFT (11U) #define CSL_SCP_TRIM_OBSERVE_REG_RTRIM_EFUSE_RESETVAL (0x00000000U) #define CSL_SCP_TRIM_OBSERVE_REG_RTRIM_EFUSE_MAX (0x0000001fU) #define CSL_SCP_TRIM_OBSERVE_REG_SPAREBITS_SHANTANUTX_TRIM_OBSERVE_REG_MASK (0x000007FFU) #define CSL_SCP_TRIM_OBSERVE_REG_SPAREBITS_SHANTANUTX_TRIM_OBSERVE_REG_SHIFT (0U) #define CSL_SCP_TRIM_OBSERVE_REG_SPAREBITS_SHANTANUTX_TRIM_OBSERVE_REG_RESETVAL (0x00000000U) #define CSL_SCP_TRIM_OBSERVE_REG_SPAREBITS_SHANTANUTX_TRIM_OBSERVE_REG_MAX (0x000007ffU) #define CSL_SCP_TRIM_OBSERVE_REG_RESETVAL (0x00000000U) /* IO_OVERRIDE_REG */ #define CSL_SCP_IO_OVERRIDE_REG_MEM_PLLOP_LOCK_MASK (0x80000000U) #define CSL_SCP_IO_OVERRIDE_REG_MEM_PLLOP_LOCK_SHIFT (31U) #define CSL_SCP_IO_OVERRIDE_REG_MEM_PLLOP_LOCK_RESETVAL (0x00000000U) #define CSL_SCP_IO_OVERRIDE_REG_MEM_PLLOP_LOCK_MAX (0x00000001U) #define CSL_SCP_IO_OVERRIDE_REG_MEM_OVRD_PLLOP_LOCK_MASK (0x40000000U) #define CSL_SCP_IO_OVERRIDE_REG_MEM_OVRD_PLLOP_LOCK_SHIFT (30U) #define CSL_SCP_IO_OVERRIDE_REG_MEM_OVRD_PLLOP_LOCK_RESETVAL (0x00000000U) #define CSL_SCP_IO_OVERRIDE_REG_MEM_OVRD_PLLOP_LOCK_MAX (0x00000001U) #define CSL_SCP_IO_OVERRIDE_REG_MEM_LSDATA_MASK (0x20000000U) #define CSL_SCP_IO_OVERRIDE_REG_MEM_LSDATA_SHIFT (29U) #define CSL_SCP_IO_OVERRIDE_REG_MEM_LSDATA_RESETVAL (0x00000000U) #define CSL_SCP_IO_OVERRIDE_REG_MEM_LSDATA_MAX (0x00000001U) #define CSL_SCP_IO_OVERRIDE_REG_MEM_OVRD_LSDATA_MASK (0x10000000U) #define CSL_SCP_IO_OVERRIDE_REG_MEM_OVRD_LSDATA_SHIFT (28U) #define CSL_SCP_IO_OVERRIDE_REG_MEM_OVRD_LSDATA_RESETVAL (0x00000000U) #define CSL_SCP_IO_OVERRIDE_REG_MEM_OVRD_LSDATA_MAX (0x00000001U) #define CSL_SCP_IO_OVERRIDE_REG_MEM_RX_DET_OUT_MASK (0x08000000U) #define CSL_SCP_IO_OVERRIDE_REG_MEM_RX_DET_OUT_SHIFT (27U) #define CSL_SCP_IO_OVERRIDE_REG_MEM_RX_DET_OUT_RESETVAL (0x00000000U) #define CSL_SCP_IO_OVERRIDE_REG_MEM_RX_DET_OUT_MAX (0x00000001U) #define CSL_SCP_IO_OVERRIDE_REG_MEM_OVRD_RX_DET_OUT_MASK (0x04000000U) #define CSL_SCP_IO_OVERRIDE_REG_MEM_OVRD_RX_DET_OUT_SHIFT (26U) #define CSL_SCP_IO_OVERRIDE_REG_MEM_OVRD_RX_DET_OUT_RESETVAL (0x00000000U) #define CSL_SCP_IO_OVERRIDE_REG_MEM_OVRD_RX_DET_OUT_MAX (0x00000001U) #define CSL_SCP_IO_OVERRIDE_REG_MEM_TXDLDO_STBL_OUT_MASK (0x02000000U) #define CSL_SCP_IO_OVERRIDE_REG_MEM_TXDLDO_STBL_OUT_SHIFT (25U) #define CSL_SCP_IO_OVERRIDE_REG_MEM_TXDLDO_STBL_OUT_RESETVAL (0x00000000U) #define CSL_SCP_IO_OVERRIDE_REG_MEM_TXDLDO_STBL_OUT_MAX (0x00000001U) #define CSL_SCP_IO_OVERRIDE_REG_MEM_OVRD_TXDLDO_STBL_OUT_MASK (0x01000000U) #define CSL_SCP_IO_OVERRIDE_REG_MEM_OVRD_TXDLDO_STBL_OUT_SHIFT (24U) #define CSL_SCP_IO_OVERRIDE_REG_MEM_OVRD_TXDLDO_STBL_OUT_RESETVAL (0x00000000U) #define CSL_SCP_IO_OVERRIDE_REG_MEM_OVRD_TXDLDO_STBL_OUT_MAX (0x00000001U) #define CSL_SCP_IO_OVERRIDE_REG_MEM_TXALDO_STBL_OUT_MASK (0x00800000U) #define CSL_SCP_IO_OVERRIDE_REG_MEM_TXALDO_STBL_OUT_SHIFT (23U) #define CSL_SCP_IO_OVERRIDE_REG_MEM_TXALDO_STBL_OUT_RESETVAL (0x00000000U) #define CSL_SCP_IO_OVERRIDE_REG_MEM_TXALDO_STBL_OUT_MAX (0x00000001U) #define CSL_SCP_IO_OVERRIDE_REG_MEM_OVRD_TXALDO_STBL_OUT_MASK (0x00400000U) #define CSL_SCP_IO_OVERRIDE_REG_MEM_OVRD_TXALDO_STBL_OUT_SHIFT (22U) #define CSL_SCP_IO_OVERRIDE_REG_MEM_OVRD_TXALDO_STBL_OUT_RESETVAL (0x00000000U) #define CSL_SCP_IO_OVERRIDE_REG_MEM_OVRD_TXALDO_STBL_OUT_MAX (0x00000001U) #define CSL_SCP_IO_OVERRIDE_REG_MEM_SPAREBITS_SHANTANUTX_IO_OVERRIDE_REG_MASK (0x003FFFFFU) #define CSL_SCP_IO_OVERRIDE_REG_MEM_SPAREBITS_SHANTANUTX_IO_OVERRIDE_REG_SHIFT (0U) #define CSL_SCP_IO_OVERRIDE_REG_MEM_SPAREBITS_SHANTANUTX_IO_OVERRIDE_REG_RESETVAL (0x00000000U) #define CSL_SCP_IO_OVERRIDE_REG_MEM_SPAREBITS_SHANTANUTX_IO_OVERRIDE_REG_MAX (0x003fffffU) #define CSL_SCP_IO_OVERRIDE_REG_RESETVAL (0x00000000U) /* TEST_CONFIG_REG */ #define CSL_SCP_TEST_CONFIG_REG_MEM_ENTESTCLK_MASK (0x80000000U) #define CSL_SCP_TEST_CONFIG_REG_MEM_ENTESTCLK_SHIFT (31U) #define CSL_SCP_TEST_CONFIG_REG_MEM_ENTESTCLK_RESETVAL (0x00000000U) #define CSL_SCP_TEST_CONFIG_REG_MEM_ENTESTCLK_MAX (0x00000001U) #define CSL_SCP_TEST_CONFIG_REG_MEM_EN_LPBK_MASK (0x40000000U) #define CSL_SCP_TEST_CONFIG_REG_MEM_EN_LPBK_SHIFT (30U) #define CSL_SCP_TEST_CONFIG_REG_MEM_EN_LPBK_RESETVAL (0x00000000U) #define CSL_SCP_TEST_CONFIG_REG_MEM_EN_LPBK_MAX (0x00000001U) #define CSL_SCP_TEST_CONFIG_REG_MEM_ENTXPATT_MASK (0x20000000U) #define CSL_SCP_TEST_CONFIG_REG_MEM_ENTXPATT_SHIFT (29U) #define CSL_SCP_TEST_CONFIG_REG_MEM_ENTXPATT_RESETVAL (0x00000000U) #define CSL_SCP_TEST_CONFIG_REG_MEM_ENTXPATT_MAX (0x00000001U) #define CSL_SCP_TEST_CONFIG_REG_MEM_TESTPATT_MASK (0x1C000000U) #define CSL_SCP_TEST_CONFIG_REG_MEM_TESTPATT_SHIFT (26U) #define CSL_SCP_TEST_CONFIG_REG_MEM_TESTPATT_RESETVAL (0x00000000U) #define CSL_SCP_TEST_CONFIG_REG_MEM_TESTPATT_MAX (0x00000007U) #define CSL_SCP_TEST_CONFIG_REG_MEM_AMUX_CTRL_MASK (0x03C00000U) #define CSL_SCP_TEST_CONFIG_REG_MEM_AMUX_CTRL_SHIFT (22U) #define CSL_SCP_TEST_CONFIG_REG_MEM_AMUX_CTRL_RESETVAL (0x00000000U) #define CSL_SCP_TEST_CONFIG_REG_MEM_AMUX_CTRL_MAX (0x0000000fU) #define CSL_SCP_TEST_CONFIG_REG_MEM_EN_TXBCLK_DIV_MASK (0x00200000U) #define CSL_SCP_TEST_CONFIG_REG_MEM_EN_TXBCLK_DIV_SHIFT (21U) #define CSL_SCP_TEST_CONFIG_REG_MEM_EN_TXBCLK_DIV_RESETVAL (0x00000000U) #define CSL_SCP_TEST_CONFIG_REG_MEM_EN_TXBCLK_DIV_MAX (0x00000001U) #define CSL_SCP_TEST_CONFIG_REG_MEM_SPAREBITS_SHANTANUTX_TEST_CONFIG_REG_MASK (0x001FFFFFU) #define CSL_SCP_TEST_CONFIG_REG_MEM_SPAREBITS_SHANTANUTX_TEST_CONFIG_REG_SHIFT (0U) #define CSL_SCP_TEST_CONFIG_REG_MEM_SPAREBITS_SHANTANUTX_TEST_CONFIG_REG_RESETVAL (0x00000000U) #define CSL_SCP_TEST_CONFIG_REG_MEM_SPAREBITS_SHANTANUTX_TEST_CONFIG_REG_MAX (0x001fffffU) #define CSL_SCP_TEST_CONFIG_REG_RESETVAL (0x00000000U) /* PATTGEN_PRELOAD */ #define CSL_SCP_PATTGEN_PRELOAD_MEM_PATTGEN_PRELOAD_VAL_MASK (0xFFFFFFFEU) #define CSL_SCP_PATTGEN_PRELOAD_MEM_PATTGEN_PRELOAD_VAL_SHIFT (1U) #define CSL_SCP_PATTGEN_PRELOAD_MEM_PATTGEN_PRELOAD_VAL_RESETVAL (0x00000000U) #define CSL_SCP_PATTGEN_PRELOAD_MEM_PATTGEN_PRELOAD_VAL_MAX (0x7fffffffU) #define CSL_SCP_PATTGEN_PRELOAD_MEM_SPAREBITS_SHANTANUTX_PATTGEN_PRELOAD_MASK (0x00000001U) #define CSL_SCP_PATTGEN_PRELOAD_MEM_SPAREBITS_SHANTANUTX_PATTGEN_PRELOAD_SHIFT (0U) #define CSL_SCP_PATTGEN_PRELOAD_MEM_SPAREBITS_SHANTANUTX_PATTGEN_PRELOAD_RESETVAL (0x00000000U) #define CSL_SCP_PATTGEN_PRELOAD_MEM_SPAREBITS_SHANTANUTX_PATTGEN_PRELOAD_MAX (0x00000001U) #define CSL_SCP_PATTGEN_PRELOAD_RESETVAL (0x00000000U) /* DFT_OBSERVE_REG1 */ #define CSL_SCP_DFT_OBSERVE_REG1_EN_BG_RD_MASK (0x80000000U) #define CSL_SCP_DFT_OBSERVE_REG1_EN_BG_RD_SHIFT (31U) #define CSL_SCP_DFT_OBSERVE_REG1_EN_BG_RD_RESETVAL (0x00000000U) #define CSL_SCP_DFT_OBSERVE_REG1_EN_BG_RD_MAX (0x00000001U) #define CSL_SCP_DFT_OBSERVE_REG1_EN_DCC_SCP_RD_MASK (0x40000000U) #define CSL_SCP_DFT_OBSERVE_REG1_EN_DCC_SCP_RD_SHIFT (30U) #define CSL_SCP_DFT_OBSERVE_REG1_EN_DCC_SCP_RD_RESETVAL (0x00000000U) #define CSL_SCP_DFT_OBSERVE_REG1_EN_DCC_SCP_RD_MAX (0x00000001U) #define CSL_SCP_DFT_OBSERVE_REG1_EN_IDLE_RD_MASK (0x20000000U) #define CSL_SCP_DFT_OBSERVE_REG1_EN_IDLE_RD_SHIFT (29U) #define CSL_SCP_DFT_OBSERVE_REG1_EN_IDLE_RD_RESETVAL (0x00000000U) #define CSL_SCP_DFT_OBSERVE_REG1_EN_IDLE_RD_MAX (0x00000001U) #define CSL_SCP_DFT_OBSERVE_REG1_EN_LFPS_RD_MASK (0x10000000U) #define CSL_SCP_DFT_OBSERVE_REG1_EN_LFPS_RD_SHIFT (28U) #define CSL_SCP_DFT_OBSERVE_REG1_EN_LFPS_RD_RESETVAL (0x00000000U) #define CSL_SCP_DFT_OBSERVE_REG1_EN_LFPS_RD_MAX (0x00000001U) #define CSL_SCP_DFT_OBSERVE_REG1_EN_LOWSWING_RD_MASK (0x08000000U) #define CSL_SCP_DFT_OBSERVE_REG1_EN_LOWSWING_RD_SHIFT (27U) #define CSL_SCP_DFT_OBSERVE_REG1_EN_LOWSWING_RD_RESETVAL (0x00000000U) #define CSL_SCP_DFT_OBSERVE_REG1_EN_LOWSWING_RD_MAX (0x00000001U) #define CSL_SCP_DFT_OBSERVE_REG1_EN_RX_DETECT_RD_MASK (0x06000000U) #define CSL_SCP_DFT_OBSERVE_REG1_EN_RX_DETECT_RD_SHIFT (25U) #define CSL_SCP_DFT_OBSERVE_REG1_EN_RX_DETECT_RD_RESETVAL (0x00000000U) #define CSL_SCP_DFT_OBSERVE_REG1_EN_RX_DETECT_RD_MAX (0x00000003U) #define CSL_SCP_DFT_OBSERVE_REG1_EN_TXA_RD_MASK (0x01000000U) #define CSL_SCP_DFT_OBSERVE_REG1_EN_TXA_RD_SHIFT (24U) #define CSL_SCP_DFT_OBSERVE_REG1_EN_TXA_RD_RESETVAL (0x00000000U) #define CSL_SCP_DFT_OBSERVE_REG1_EN_TXA_RD_MAX (0x00000001U) #define CSL_SCP_DFT_OBSERVE_REG1_EN_TXALDO_RD_MASK (0x00800000U) #define CSL_SCP_DFT_OBSERVE_REG1_EN_TXALDO_RD_SHIFT (23U) #define CSL_SCP_DFT_OBSERVE_REG1_EN_TXALDO_RD_RESETVAL (0x00000000U) #define CSL_SCP_DFT_OBSERVE_REG1_EN_TXALDO_RD_MAX (0x00000001U) #define CSL_SCP_DFT_OBSERVE_REG1_EN_TXDLDO_RD_MASK (0x00400000U) #define CSL_SCP_DFT_OBSERVE_REG1_EN_TXDLDO_RD_SHIFT (22U) #define CSL_SCP_DFT_OBSERVE_REG1_EN_TXDLDO_RD_RESETVAL (0x00000000U) #define CSL_SCP_DFT_OBSERVE_REG1_EN_TXDLDO_RD_MAX (0x00000001U) #define CSL_SCP_DFT_OBSERVE_REG1_EN_TX_RD_MASK (0x00200000U) #define CSL_SCP_DFT_OBSERVE_REG1_EN_TX_RD_SHIFT (21U) #define CSL_SCP_DFT_OBSERVE_REG1_EN_TX_RD_RESETVAL (0x00000000U) #define CSL_SCP_DFT_OBSERVE_REG1_EN_TX_RD_MAX (0x00000001U) #define CSL_SCP_DFT_OBSERVE_REG1_EN_TXREG_RD_MASK (0x00100000U) #define CSL_SCP_DFT_OBSERVE_REG1_EN_TXREG_RD_SHIFT (20U) #define CSL_SCP_DFT_OBSERVE_REG1_EN_TXREG_RD_RESETVAL (0x00000000U) #define CSL_SCP_DFT_OBSERVE_REG1_EN_TXREG_RD_MAX (0x00000001U) #define CSL_SCP_DFT_OBSERVE_REG1_EN_SYNC_PULSE_RD_MASK (0x00080000U) #define CSL_SCP_DFT_OBSERVE_REG1_EN_SYNC_PULSE_RD_SHIFT (19U) #define CSL_SCP_DFT_OBSERVE_REG1_EN_SYNC_PULSE_RD_RESETVAL (0x00000000U) #define CSL_SCP_DFT_OBSERVE_REG1_EN_SYNC_PULSE_RD_MAX (0x00000001U) #define CSL_SCP_DFT_OBSERVE_REG1_ISO_LDODOMAIN_RD_MASK (0x00040000U) #define CSL_SCP_DFT_OBSERVE_REG1_ISO_LDODOMAIN_RD_SHIFT (18U) #define CSL_SCP_DFT_OBSERVE_REG1_ISO_LDODOMAIN_RD_RESETVAL (0x00000000U) #define CSL_SCP_DFT_OBSERVE_REG1_ISO_LDODOMAIN_RD_MAX (0x00000001U) #define CSL_SCP_DFT_OBSERVE_REG1_RSTN_LDODOMAIN_RD_MASK (0x00020000U) #define CSL_SCP_DFT_OBSERVE_REG1_RSTN_LDODOMAIN_RD_SHIFT (17U) #define CSL_SCP_DFT_OBSERVE_REG1_RSTN_LDODOMAIN_RD_RESETVAL (0x00000000U) #define CSL_SCP_DFT_OBSERVE_REG1_RSTN_LDODOMAIN_RD_MAX (0x00000001U) #define CSL_SCP_DFT_OBSERVE_REG1_HS_RATE_RD_MASK (0x00018000U) #define CSL_SCP_DFT_OBSERVE_REG1_HS_RATE_RD_SHIFT (15U) #define CSL_SCP_DFT_OBSERVE_REG1_HS_RATE_RD_RESETVAL (0x00000000U) #define CSL_SCP_DFT_OBSERVE_REG1_HS_RATE_RD_MAX (0x00000003U) #define CSL_SCP_DFT_OBSERVE_REG1_SWING_RD_MASK (0x00007800U) #define CSL_SCP_DFT_OBSERVE_REG1_SWING_RD_SHIFT (11U) #define CSL_SCP_DFT_OBSERVE_REG1_SWING_RD_RESETVAL (0x00000000U) #define CSL_SCP_DFT_OBSERVE_REG1_SWING_RD_MAX (0x0000000fU) #define CSL_SCP_DFT_OBSERVE_REG1_STD_RD_MASK (0x00000700U) #define CSL_SCP_DFT_OBSERVE_REG1_STD_RD_SHIFT (8U) #define CSL_SCP_DFT_OBSERVE_REG1_STD_RD_RESETVAL (0x00000000U) #define CSL_SCP_DFT_OBSERVE_REG1_STD_RD_MAX (0x00000007U) #define CSL_SCP_DFT_OBSERVE_REG1_PLLOP_LOCK_RD_MASK (0x00000080U) #define CSL_SCP_DFT_OBSERVE_REG1_PLLOP_LOCK_RD_SHIFT (7U) #define CSL_SCP_DFT_OBSERVE_REG1_PLLOP_LOCK_RD_RESETVAL (0x00000000U) #define CSL_SCP_DFT_OBSERVE_REG1_PLLOP_LOCK_RD_MAX (0x00000001U) #define CSL_SCP_DFT_OBSERVE_REG1_LSDATA_RD_MASK (0x00000040U) #define CSL_SCP_DFT_OBSERVE_REG1_LSDATA_RD_SHIFT (6U) #define CSL_SCP_DFT_OBSERVE_REG1_LSDATA_RD_RESETVAL (0x00000000U) #define CSL_SCP_DFT_OBSERVE_REG1_LSDATA_RD_MAX (0x00000001U) #define CSL_SCP_DFT_OBSERVE_REG1_DE_RD_MASK (0x0000003EU) #define CSL_SCP_DFT_OBSERVE_REG1_DE_RD_SHIFT (1U) #define CSL_SCP_DFT_OBSERVE_REG1_DE_RD_RESETVAL (0x00000000U) #define CSL_SCP_DFT_OBSERVE_REG1_DE_RD_MAX (0x0000001fU) #define CSL_SCP_DFT_OBSERVE_REG1_PHOLDL_RD_MASK (0x00000001U) #define CSL_SCP_DFT_OBSERVE_REG1_PHOLDL_RD_SHIFT (0U) #define CSL_SCP_DFT_OBSERVE_REG1_PHOLDL_RD_RESETVAL (0x00000000U) #define CSL_SCP_DFT_OBSERVE_REG1_PHOLDL_RD_MAX (0x00000001U) #define CSL_SCP_DFT_OBSERVE_REG1_RESETVAL (0x00000000U) #ifdef __cplusplus } #endif #endif