/******************************************************************** * Copyright (C) 2013-2014 Texas Instruments Incorporated. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * */ #ifndef CSLR_GPU_H_ #define CSLR_GPU_H_ #ifdef __cplusplus extern "C" { #endif #include #include /************************************************************************** * Register Overlay Structure for ALL **************************************************************************/ typedef struct { volatile Uint32 REVISION; volatile Uint32 HWINFO; volatile Uint8 RSVD0[8]; volatile Uint32 SYSCONFIG; volatile Uint8 RSVD1[16]; volatile Uint32 IRQSTATUS_RAW_0; volatile Uint32 IRQSTATUS_RAW_1; volatile Uint32 IRQSTATUS_RAW_2; volatile Uint32 IRQSTATUS_0; volatile Uint32 IRQSTATUS_1; volatile Uint32 IRQSTATUS_2; volatile Uint32 IRQENABLE_SET_0; volatile Uint32 IRQENABLE_SET_1; volatile Uint32 IRQENABLE_SET_2; volatile Uint32 IRQENABLE_CLR_0; volatile Uint32 IRQENABLE_CLR_1; volatile Uint32 IRQENABLE_CLR_2; volatile Uint8 RSVD2[172]; volatile Uint32 PAGE_CONFIG; volatile Uint32 INTERRUPT_EVENT; volatile Uint32 DEBUG_CONFIG; volatile Uint32 DEBUG_STATUS_0; volatile Uint32 DEBUG_STATUS_1; volatile Uint8 RSVD3[236]; } CSL_GpuRegs; /************************************************************************** * Register Macros **************************************************************************/ /* See IPG spec for more details. */ #define CSL_GPU_REVISION (0x0U) /* HWINFO */ #define CSL_GPU_HWINFO (0x4U) /* SYSCONFIG */ #define CSL_GPU_SYSCONFIG (0x10U) /* IRQSTATUS_RAW_0 */ #define CSL_GPU_IRQSTATUS_RAW_0 (0x24U) /* IRQSTATUS_RAW_1 */ #define CSL_GPU_IRQSTATUS_RAW_1 (0x28U) /* IRQSTATUS_RAW_2 */ #define CSL_GPU_IRQSTATUS_RAW_2 (0x2CU) /* IRQSTATUS_0 */ #define CSL_GPU_IRQSTATUS_0 (0x30U) /* IRQSTATUS_1 */ #define CSL_GPU_IRQSTATUS_1 (0x34U) /* IRQSTATUS_2 */ #define CSL_GPU_IRQSTATUS_2 (0x38U) /* IRQENABLE_SET_0 */ #define CSL_GPU_IRQENABLE_SET_0 (0x3CU) /* IRQENABLE_SET_1 */ #define CSL_GPU_IRQENABLE_SET_1 (0x40U) /* IRQENABLE_SET_2 */ #define CSL_GPU_IRQENABLE_SET_2 (0x44U) /* IRQENABLE_CLR_0 */ #define CSL_GPU_IRQENABLE_CLR_0 (0x48U) /* IRQENABLE_CLR_1 */ #define CSL_GPU_IRQENABLE_CLR_1 (0x4CU) /* IRQENABLE_CLR_2 */ #define CSL_GPU_IRQENABLE_CLR_2 (0x50U) /* PAGE_CONFIG */ #define CSL_GPU_PAGE_CONFIG (0x100U) /* INTERRUPT_EVENT */ #define CSL_GPU_INTERRUPT_EVENT (0x104U) /* DEBUG_CONFIG */ #define CSL_GPU_DEBUG_CONFIG (0x108U) /* Port0 Debug Status Register */ #define CSL_GPU_DEBUG_STATUS_0 (0x10CU) /* Port1 Debug Status Register */ #define CSL_GPU_DEBUG_STATUS_1 (0x110U) /************************************************************************** * Field Definition Macros **************************************************************************/ /* REVISION */ #define CSL_GPU_REVISION_RESETVAL (0x40000000U) /* HWINFO */ #define CSL_GPU_HWINFO_MEM_BUS_WIDTH_MASK (0x00000004U) #define CSL_GPU_HWINFO_MEM_BUS_WIDTH_SHIFT (2U) #define CSL_GPU_HWINFO_MEM_BUS_WIDTH_RESETVAL (0x00000001U) #define CSL_GPU_HWINFO_MEM_BUS_WIDTH_MAX (0x00000001U) #define CSL_GPU_HWINFO_SYS_BUS_WIDTH_MASK (0x00000003U) #define CSL_GPU_HWINFO_SYS_BUS_WIDTH_SHIFT (0U) #define CSL_GPU_HWINFO_SYS_BUS_WIDTH_RESETVAL (0x00000001U) #define CSL_GPU_HWINFO_SYS_BUS_WIDTH_MAX (0x00000003U) #define CSL_GPU_HWINFO_RESETVAL (0x00000005U) /* SYSCONFIG */ #define CSL_GPU_SYSCONFIG_STANDBY_MODE_MASK (0x00000030U) #define CSL_GPU_SYSCONFIG_STANDBY_MODE_SHIFT (4U) #define CSL_GPU_SYSCONFIG_STANDBY_MODE_RESETVAL (0x00000002U) #define CSL_GPU_SYSCONFIG_STANDBY_MODE_MAX (0x00000003U) #define CSL_GPU_SYSCONFIG_IDLE_MODE_MASK (0x0000000CU) #define CSL_GPU_SYSCONFIG_IDLE_MODE_SHIFT (2U) #define CSL_GPU_SYSCONFIG_IDLE_MODE_RESETVAL (0x00000002U) #define CSL_GPU_SYSCONFIG_IDLE_MODE_MAX (0x00000003U) #define CSL_GPU_SYSCONFIG_RESETVAL (0x00000028U) /* IRQSTATUS_RAW_0 */ #define CSL_GPU_IRQSTATUS_RAW_0_INIT_MINTERRUPT_RAW_MASK (0x00000001U) #define CSL_GPU_IRQSTATUS_RAW_0_INIT_MINTERRUPT_RAW_SHIFT (0U) #define CSL_GPU_IRQSTATUS_RAW_0_INIT_MINTERRUPT_RAW_RESETVAL (0x00000000U) #define CSL_GPU_IRQSTATUS_RAW_0_INIT_MINTERRUPT_RAW_MAX (0x00000001U) #define CSL_GPU_IRQSTATUS_RAW_0_RESETVAL (0x00000000U) /* IRQSTATUS_RAW_1 */ #define CSL_GPU_IRQSTATUS_RAW_1_TARGET_SINTERRUPT_RAW_MASK (0x00000001U) #define CSL_GPU_IRQSTATUS_RAW_1_TARGET_SINTERRUPT_RAW_SHIFT (0U) #define CSL_GPU_IRQSTATUS_RAW_1_TARGET_SINTERRUPT_RAW_RESETVAL (0x00000000U) #define CSL_GPU_IRQSTATUS_RAW_1_TARGET_SINTERRUPT_RAW_MAX (0x00000001U) #define CSL_GPU_IRQSTATUS_RAW_1_RESETVAL (0x00000000U) /* IRQSTATUS_RAW_2 */ #define CSL_GPU_IRQSTATUS_RAW_2_THALIA_IRQ_RAW_MASK (0x00000001U) #define CSL_GPU_IRQSTATUS_RAW_2_THALIA_IRQ_RAW_SHIFT (0U) #define CSL_GPU_IRQSTATUS_RAW_2_THALIA_IRQ_RAW_RESETVAL (0x00000000U) #define CSL_GPU_IRQSTATUS_RAW_2_THALIA_IRQ_RAW_MAX (0x00000001U) #define CSL_GPU_IRQSTATUS_RAW_2_RESETVAL (0x00000000U) /* IRQSTATUS_0 */ #define CSL_GPU_IRQSTATUS_0_INIT_MINTERRUPT_STATUS_MASK (0x00000001U) #define CSL_GPU_IRQSTATUS_0_INIT_MINTERRUPT_STATUS_SHIFT (0U) #define CSL_GPU_IRQSTATUS_0_INIT_MINTERRUPT_STATUS_RESETVAL (0x00000000U) #define CSL_GPU_IRQSTATUS_0_INIT_MINTERRUPT_STATUS_MAX (0x00000001U) #define CSL_GPU_IRQSTATUS_0_RESETVAL (0x00000000U) /* IRQSTATUS_1 */ #define CSL_GPU_IRQSTATUS_1_TARGET_SINTERRUPT_STATUS_MASK (0x00000001U) #define CSL_GPU_IRQSTATUS_1_TARGET_SINTERRUPT_STATUS_SHIFT (0U) #define CSL_GPU_IRQSTATUS_1_TARGET_SINTERRUPT_STATUS_RESETVAL (0x00000000U) #define CSL_GPU_IRQSTATUS_1_TARGET_SINTERRUPT_STATUS_MAX (0x00000001U) #define CSL_GPU_IRQSTATUS_1_RESETVAL (0x00000000U) /* IRQSTATUS_2 */ #define CSL_GPU_IRQSTATUS_2_THALIA_IRQ_STATUS_MASK (0x00000001U) #define CSL_GPU_IRQSTATUS_2_THALIA_IRQ_STATUS_SHIFT (0U) #define CSL_GPU_IRQSTATUS_2_THALIA_IRQ_STATUS_RESETVAL (0x00000000U) #define CSL_GPU_IRQSTATUS_2_THALIA_IRQ_STATUS_MAX (0x00000001U) #define CSL_GPU_IRQSTATUS_2_RESETVAL (0x00000000U) /* IRQENABLE_SET_0 */ #define CSL_GPU_IRQENABLE_SET_0_INIT_MINTERRUPT_ENABLE_MASK (0x00000001U) #define CSL_GPU_IRQENABLE_SET_0_INIT_MINTERRUPT_ENABLE_SHIFT (0U) #define CSL_GPU_IRQENABLE_SET_0_INIT_MINTERRUPT_ENABLE_RESETVAL (0x00000000U) #define CSL_GPU_IRQENABLE_SET_0_INIT_MINTERRUPT_ENABLE_MAX (0x00000001U) #define CSL_GPU_IRQENABLE_SET_0_RESETVAL (0x00000000U) /* IRQENABLE_SET_1 */ #define CSL_GPU_IRQENABLE_SET_1_TARGET_SINTERRUPT_ENABLE_MASK (0x00000001U) #define CSL_GPU_IRQENABLE_SET_1_TARGET_SINTERRUPT_ENABLE_SHIFT (0U) #define CSL_GPU_IRQENABLE_SET_1_TARGET_SINTERRUPT_ENABLE_RESETVAL (0x00000000U) #define CSL_GPU_IRQENABLE_SET_1_TARGET_SINTERRUPT_ENABLE_MAX (0x00000001U) #define CSL_GPU_IRQENABLE_SET_1_RESETVAL (0x00000000U) /* IRQENABLE_SET_2 */ #define CSL_GPU_IRQENABLE_SET_2_THALIA_IRQ_ENABLE_MASK (0x00000001U) #define CSL_GPU_IRQENABLE_SET_2_THALIA_IRQ_ENABLE_SHIFT (0U) #define CSL_GPU_IRQENABLE_SET_2_THALIA_IRQ_ENABLE_RESETVAL (0x00000000U) #define CSL_GPU_IRQENABLE_SET_2_THALIA_IRQ_ENABLE_MAX (0x00000001U) #define CSL_GPU_IRQENABLE_SET_2_RESETVAL (0x00000000U) /* IRQENABLE_CLR_0 */ #define CSL_GPU_IRQENABLE_CLR_0_INIT_MINTERRUPT_DISABLE_MASK (0x00000001U) #define CSL_GPU_IRQENABLE_CLR_0_INIT_MINTERRUPT_DISABLE_SHIFT (0U) #define CSL_GPU_IRQENABLE_CLR_0_INIT_MINTERRUPT_DISABLE_RESETVAL (0x00000000U) #define CSL_GPU_IRQENABLE_CLR_0_INIT_MINTERRUPT_DISABLE_MAX (0x00000001U) #define CSL_GPU_IRQENABLE_CLR_0_RESETVAL (0x00000000U) /* IRQENABLE_CLR_1 */ #define CSL_GPU_IRQENABLE_CLR_1_TARGET_SINTERRUPT_DISABLE_MASK (0x00000001U) #define CSL_GPU_IRQENABLE_CLR_1_TARGET_SINTERRUPT_DISABLE_SHIFT (0U) #define CSL_GPU_IRQENABLE_CLR_1_TARGET_SINTERRUPT_DISABLE_RESETVAL (0x00000000U) #define CSL_GPU_IRQENABLE_CLR_1_TARGET_SINTERRUPT_DISABLE_MAX (0x00000001U) #define CSL_GPU_IRQENABLE_CLR_1_RESETVAL (0x00000000U) /* IRQENABLE_CLR_2 */ #define CSL_GPU_IRQENABLE_CLR_2_THALIA_IRQ_DISABLE_MASK (0x00000001U) #define CSL_GPU_IRQENABLE_CLR_2_THALIA_IRQ_DISABLE_SHIFT (0U) #define CSL_GPU_IRQENABLE_CLR_2_THALIA_IRQ_DISABLE_RESETVAL (0x00000000U) #define CSL_GPU_IRQENABLE_CLR_2_THALIA_IRQ_DISABLE_MAX (0x00000001U) #define CSL_GPU_IRQENABLE_CLR_2_RESETVAL (0x00000000U) /* PAGE_CONFIG */ #define CSL_GPU_PAGE_CONFIG_THALIA_INT_BYPASS_MASK (0x80000000U) #define CSL_GPU_PAGE_CONFIG_THALIA_INT_BYPASS_SHIFT (31U) #define CSL_GPU_PAGE_CONFIG_THALIA_INT_BYPASS_RESETVAL (0x00000000U) #define CSL_GPU_PAGE_CONFIG_THALIA_INT_BYPASS_MAX (0x00000001U) #define CSL_GPU_PAGE_CONFIG_OCP_PAGE_SIZE_MASK (0x00000018U) #define CSL_GPU_PAGE_CONFIG_OCP_PAGE_SIZE_SHIFT (3U) #define CSL_GPU_PAGE_CONFIG_OCP_PAGE_SIZE_RESETVAL (0x00000002U) #define CSL_GPU_PAGE_CONFIG_OCP_PAGE_SIZE_MAX (0x00000003U) #define CSL_GPU_PAGE_CONFIG_MEM_PAGE_CHECK_EN_MASK (0x00000004U) #define CSL_GPU_PAGE_CONFIG_MEM_PAGE_CHECK_EN_SHIFT (2U) #define CSL_GPU_PAGE_CONFIG_MEM_PAGE_CHECK_EN_RESETVAL (0x00000001U) #define CSL_GPU_PAGE_CONFIG_MEM_PAGE_CHECK_EN_MAX (0x00000001U) #define CSL_GPU_PAGE_CONFIG_MEM_PAGE_SIZE_MASK (0x00000003U) #define CSL_GPU_PAGE_CONFIG_MEM_PAGE_SIZE_SHIFT (0U) #define CSL_GPU_PAGE_CONFIG_MEM_PAGE_SIZE_RESETVAL (0x00000000U) #define CSL_GPU_PAGE_CONFIG_MEM_PAGE_SIZE_MAX (0x00000003U) #define CSL_GPU_PAGE_CONFIG_RESETVAL (0x00000014U) /* INTERRUPT_EVENT */ #define CSL_GPU_INTERRUPT_EVENT_TARGET_INVALID_OCP_CMD_MASK (0x00040000U) #define CSL_GPU_INTERRUPT_EVENT_TARGET_INVALID_OCP_CMD_SHIFT (18U) #define CSL_GPU_INTERRUPT_EVENT_TARGET_INVALID_OCP_CMD_RESETVAL (0x00000000U) #define CSL_GPU_INTERRUPT_EVENT_TARGET_INVALID_OCP_CMD_MAX (0x00000001U) #define CSL_GPU_INTERRUPT_EVENT_TARGET_CMD_FIFO_FULL_MASK (0x00020000U) #define CSL_GPU_INTERRUPT_EVENT_TARGET_CMD_FIFO_FULL_SHIFT (17U) #define CSL_GPU_INTERRUPT_EVENT_TARGET_CMD_FIFO_FULL_RESETVAL (0x00000000U) #define CSL_GPU_INTERRUPT_EVENT_TARGET_CMD_FIFO_FULL_MAX (0x00000001U) #define CSL_GPU_INTERRUPT_EVENT_TARGET_RESP_FIFO_FULL_MASK (0x00010000U) #define CSL_GPU_INTERRUPT_EVENT_TARGET_RESP_FIFO_FULL_SHIFT (16U) #define CSL_GPU_INTERRUPT_EVENT_TARGET_RESP_FIFO_FULL_RESETVAL (0x00000000U) #define CSL_GPU_INTERRUPT_EVENT_TARGET_RESP_FIFO_FULL_MAX (0x00000001U) #define CSL_GPU_INTERRUPT_EVENT_INT_MEM_REQ_FIFO_OVERRUN_1_MASK (0x00002000U) #define CSL_GPU_INTERRUPT_EVENT_INT_MEM_REQ_FIFO_OVERRUN_1_SHIFT (13U) #define CSL_GPU_INTERRUPT_EVENT_INT_MEM_REQ_FIFO_OVERRUN_1_RESETVAL (0x00000000U) #define CSL_GPU_INTERRUPT_EVENT_INT_MEM_REQ_FIFO_OVERRUN_1_MAX (0x00000001U) #define CSL_GPU_INTERRUPT_EVENT_INIT_READ_TAG_FIFO_OVERRUN_1_MASK (0x00001000U) #define CSL_GPU_INTERRUPT_EVENT_INIT_READ_TAG_FIFO_OVERRUN_1_SHIFT (12U) #define CSL_GPU_INTERRUPT_EVENT_INIT_READ_TAG_FIFO_OVERRUN_1_RESETVAL (0x00000000U) #define CSL_GPU_INTERRUPT_EVENT_INIT_READ_TAG_FIFO_OVERRUN_1_MAX (0x00000001U) #define CSL_GPU_INTERRUPT_EVENT_INIT_PAGE_CROSS_ERROR_1_MASK (0x00000800U) #define CSL_GPU_INTERRUPT_EVENT_INIT_PAGE_CROSS_ERROR_1_SHIFT (11U) #define CSL_GPU_INTERRUPT_EVENT_INIT_PAGE_CROSS_ERROR_1_RESETVAL (0x00000000U) #define CSL_GPU_INTERRUPT_EVENT_INIT_PAGE_CROSS_ERROR_1_MAX (0x00000001U) #define CSL_GPU_INTERRUPT_EVENT_INIT_RESP_ERROR_1_MASK (0x00000400U) #define CSL_GPU_INTERRUPT_EVENT_INIT_RESP_ERROR_1_SHIFT (10U) #define CSL_GPU_INTERRUPT_EVENT_INIT_RESP_ERROR_1_RESETVAL (0x00000000U) #define CSL_GPU_INTERRUPT_EVENT_INIT_RESP_ERROR_1_MAX (0x00000001U) #define CSL_GPU_INTERRUPT_EVENT_INIT_RESP_UNUSED_TAG_1_MASK (0x00000200U) #define CSL_GPU_INTERRUPT_EVENT_INIT_RESP_UNUSED_TAG_1_SHIFT (9U) #define CSL_GPU_INTERRUPT_EVENT_INIT_RESP_UNUSED_TAG_1_RESETVAL (0x00000000U) #define CSL_GPU_INTERRUPT_EVENT_INIT_RESP_UNUSED_TAG_1_MAX (0x00000001U) #define CSL_GPU_INTERRUPT_EVENT_INIT_RESP_UNEXPECTED_1_MASK (0x00000100U) #define CSL_GPU_INTERRUPT_EVENT_INIT_RESP_UNEXPECTED_1_SHIFT (8U) #define CSL_GPU_INTERRUPT_EVENT_INIT_RESP_UNEXPECTED_1_RESETVAL (0x00000000U) #define CSL_GPU_INTERRUPT_EVENT_INIT_RESP_UNEXPECTED_1_MAX (0x00000001U) #define CSL_GPU_INTERRUPT_EVENT_INIT_MEM_REQ_FIFO_OVERRUN_0_MASK (0x00000020U) #define CSL_GPU_INTERRUPT_EVENT_INIT_MEM_REQ_FIFO_OVERRUN_0_SHIFT (5U) #define CSL_GPU_INTERRUPT_EVENT_INIT_MEM_REQ_FIFO_OVERRUN_0_RESETVAL (0x00000000U) #define CSL_GPU_INTERRUPT_EVENT_INIT_MEM_REQ_FIFO_OVERRUN_0_MAX (0x00000001U) #define CSL_GPU_INTERRUPT_EVENT_INIT_READ_TAG_FIFO_OVERRUN_0_MASK (0x00000010U) #define CSL_GPU_INTERRUPT_EVENT_INIT_READ_TAG_FIFO_OVERRUN_0_SHIFT (4U) #define CSL_GPU_INTERRUPT_EVENT_INIT_READ_TAG_FIFO_OVERRUN_0_RESETVAL (0x00000000U) #define CSL_GPU_INTERRUPT_EVENT_INIT_READ_TAG_FIFO_OVERRUN_0_MAX (0x00000001U) #define CSL_GPU_INTERRUPT_EVENT_INIT_PAGE_CROSS_ERROR_0_MASK (0x00000008U) #define CSL_GPU_INTERRUPT_EVENT_INIT_PAGE_CROSS_ERROR_0_SHIFT (3U) #define CSL_GPU_INTERRUPT_EVENT_INIT_PAGE_CROSS_ERROR_0_RESETVAL (0x00000000U) #define CSL_GPU_INTERRUPT_EVENT_INIT_PAGE_CROSS_ERROR_0_MAX (0x00000001U) #define CSL_GPU_INTERRUPT_EVENT_INIT_RESP_ERROR_0_MASK (0x00000004U) #define CSL_GPU_INTERRUPT_EVENT_INIT_RESP_ERROR_0_SHIFT (2U) #define CSL_GPU_INTERRUPT_EVENT_INIT_RESP_ERROR_0_RESETVAL (0x00000000U) #define CSL_GPU_INTERRUPT_EVENT_INIT_RESP_ERROR_0_MAX (0x00000001U) #define CSL_GPU_INTERRUPT_EVENT_INIT_RESP_UNUSED_TAG_0_MASK (0x00000002U) #define CSL_GPU_INTERRUPT_EVENT_INIT_RESP_UNUSED_TAG_0_SHIFT (1U) #define CSL_GPU_INTERRUPT_EVENT_INIT_RESP_UNUSED_TAG_0_RESETVAL (0x00000000U) #define CSL_GPU_INTERRUPT_EVENT_INIT_RESP_UNUSED_TAG_0_MAX (0x00000001U) #define CSL_GPU_INTERRUPT_EVENT_INIT_RESP_UNEXPECTED_0_MASK (0x00000001U) #define CSL_GPU_INTERRUPT_EVENT_INIT_RESP_UNEXPECTED_0_SHIFT (0U) #define CSL_GPU_INTERRUPT_EVENT_INIT_RESP_UNEXPECTED_0_RESETVAL (0x00000000U) #define CSL_GPU_INTERRUPT_EVENT_INIT_RESP_UNEXPECTED_0_MAX (0x00000001U) #define CSL_GPU_INTERRUPT_EVENT_RESETVAL (0x00000000U) /* DEBUG_CONFIG */ #define CSL_GPU_DEBUG_CONFIG_SELECT_INT_IDLE_MASK (0x00000020U) #define CSL_GPU_DEBUG_CONFIG_SELECT_INT_IDLE_SHIFT (5U) #define CSL_GPU_DEBUG_CONFIG_SELECT_INT_IDLE_RESETVAL (0x00000000U) #define CSL_GPU_DEBUG_CONFIG_SELECT_INT_IDLE_MAX (0x00000001U) #define CSL_GPU_DEBUG_CONFIG_FORCE_PASS_DATA_MASK (0x00000010U) #define CSL_GPU_DEBUG_CONFIG_FORCE_PASS_DATA_SHIFT (4U) #define CSL_GPU_DEBUG_CONFIG_FORCE_PASS_DATA_RESETVAL (0x00000000U) #define CSL_GPU_DEBUG_CONFIG_FORCE_PASS_DATA_MAX (0x00000001U) #define CSL_GPU_DEBUG_CONFIG_FORCE_INIT_IDLE_MASK (0x0000000CU) #define CSL_GPU_DEBUG_CONFIG_FORCE_INIT_IDLE_SHIFT (2U) #define CSL_GPU_DEBUG_CONFIG_FORCE_INIT_IDLE_RESETVAL (0x00000000U) #define CSL_GPU_DEBUG_CONFIG_FORCE_INIT_IDLE_MAX (0x00000003U) #define CSL_GPU_DEBUG_CONFIG_FORCE_TARGET_IDLE_MASK (0x00000003U) #define CSL_GPU_DEBUG_CONFIG_FORCE_TARGET_IDLE_SHIFT (0U) #define CSL_GPU_DEBUG_CONFIG_FORCE_TARGET_IDLE_RESETVAL (0x00000000U) #define CSL_GPU_DEBUG_CONFIG_FORCE_TARGET_IDLE_MAX (0x00000003U) #define CSL_GPU_DEBUG_CONFIG_RESETVAL (0x00000000U) /* DEBUG_STATUS_0 */ #define CSL_GPU_DEBUG_STATUS_0_CMD_DEBUG_STATE_MASK (0x80000000U) #define CSL_GPU_DEBUG_STATUS_0_CMD_DEBUG_STATE_SHIFT (31U) #define CSL_GPU_DEBUG_STATUS_0_CMD_DEBUG_STATE_RESETVAL (0x00000000U) #define CSL_GPU_DEBUG_STATUS_0_CMD_DEBUG_STATE_MAX (0x00000001U) #define CSL_GPU_DEBUG_STATUS_0_CMD_RESP_DEBUG_STATE_MASK (0x40000000U) #define CSL_GPU_DEBUG_STATUS_0_CMD_RESP_DEBUG_STATE_SHIFT (30U) #define CSL_GPU_DEBUG_STATUS_0_CMD_RESP_DEBUG_STATE_RESETVAL (0x00000000U) #define CSL_GPU_DEBUG_STATUS_0_CMD_RESP_DEBUG_STATE_MAX (0x00000001U) #define CSL_GPU_DEBUG_STATUS_0_TARGET_IDLE_MASK (0x20000000U) #define CSL_GPU_DEBUG_STATUS_0_TARGET_IDLE_SHIFT (29U) #define CSL_GPU_DEBUG_STATUS_0_TARGET_IDLE_RESETVAL (0x00000000U) #define CSL_GPU_DEBUG_STATUS_0_TARGET_IDLE_MAX (0x00000001U) #define CSL_GPU_DEBUG_STATUS_0_RESP_FIFO_FULL_MASK (0x10000000U) #define CSL_GPU_DEBUG_STATUS_0_RESP_FIFO_FULL_SHIFT (28U) #define CSL_GPU_DEBUG_STATUS_0_RESP_FIFO_FULL_RESETVAL (0x00000000U) #define CSL_GPU_DEBUG_STATUS_0_RESP_FIFO_FULL_MAX (0x00000001U) #define CSL_GPU_DEBUG_STATUS_0_CMD_FIFO_FULL_MASK (0x08000000U) #define CSL_GPU_DEBUG_STATUS_0_CMD_FIFO_FULL_SHIFT (27U) #define CSL_GPU_DEBUG_STATUS_0_CMD_FIFO_FULL_RESETVAL (0x00000000U) #define CSL_GPU_DEBUG_STATUS_0_CMD_FIFO_FULL_MAX (0x00000001U) #define CSL_GPU_DEBUG_STATUS_0_RESP_ERROR_MASK (0x04000000U) #define CSL_GPU_DEBUG_STATUS_0_RESP_ERROR_SHIFT (26U) #define CSL_GPU_DEBUG_STATUS_0_RESP_ERROR_RESETVAL (0x00000000U) #define CSL_GPU_DEBUG_STATUS_0_RESP_ERROR_MAX (0x00000001U) #define CSL_GPU_DEBUG_STATUS_0_WHICH_TARGET_REGISTER_MASK (0x03E00000U) #define CSL_GPU_DEBUG_STATUS_0_WHICH_TARGET_REGISTER_SHIFT (21U) #define CSL_GPU_DEBUG_STATUS_0_WHICH_TARGET_REGISTER_RESETVAL (0x00000000U) #define CSL_GPU_DEBUG_STATUS_0_WHICH_TARGET_REGISTER_MAX (0x0000001fU) #define CSL_GPU_DEBUG_STATUS_0_TARGET_CMD_OUT_MASK (0x001C0000U) #define CSL_GPU_DEBUG_STATUS_0_TARGET_CMD_OUT_SHIFT (18U) #define CSL_GPU_DEBUG_STATUS_0_TARGET_CMD_OUT_RESETVAL (0x00000000U) #define CSL_GPU_DEBUG_STATUS_0_TARGET_CMD_OUT_MAX (0x00000007U) #define CSL_GPU_DEBUG_STATUS_0_INIT_MSTANDBY_MASK (0x00020000U) #define CSL_GPU_DEBUG_STATUS_0_INIT_MSTANDBY_SHIFT (17U) #define CSL_GPU_DEBUG_STATUS_0_INIT_MSTANDBY_RESETVAL (0x00000000U) #define CSL_GPU_DEBUG_STATUS_0_INIT_MSTANDBY_MAX (0x00000001U) #define CSL_GPU_DEBUG_STATUS_0_INIT_MWAIT_MASK (0x00010000U) #define CSL_GPU_DEBUG_STATUS_0_INIT_MWAIT_SHIFT (16U) #define CSL_GPU_DEBUG_STATUS_0_INIT_MWAIT_RESETVAL (0x00000000U) #define CSL_GPU_DEBUG_STATUS_0_INIT_MWAIT_MAX (0x00000001U) #define CSL_GPU_DEBUG_STATUS_0_INIT_MDISCREQ_MASK (0x00008000U) #define CSL_GPU_DEBUG_STATUS_0_INIT_MDISCREQ_SHIFT (15U) #define CSL_GPU_DEBUG_STATUS_0_INIT_MDISCREQ_RESETVAL (0x00000000U) #define CSL_GPU_DEBUG_STATUS_0_INIT_MDISCREQ_MAX (0x00000001U) #define CSL_GPU_DEBUG_STATUS_0_INIT_MDISCACK_MASK (0x00006000U) #define CSL_GPU_DEBUG_STATUS_0_INIT_MDISCACK_SHIFT (13U) #define CSL_GPU_DEBUG_STATUS_0_INIT_MDISCACK_RESETVAL (0x00000000U) #define CSL_GPU_DEBUG_STATUS_0_INIT_MDISCACK_MAX (0x00000003U) #define CSL_GPU_DEBUG_STATUS_0_INIT_SCONNECT_2_MASK (0x00001000U) #define CSL_GPU_DEBUG_STATUS_0_INIT_SCONNECT_2_SHIFT (12U) #define CSL_GPU_DEBUG_STATUS_0_INIT_SCONNECT_2_RESETVAL (0x00000000U) #define CSL_GPU_DEBUG_STATUS_0_INIT_SCONNECT_2_MAX (0x00000001U) #define CSL_GPU_DEBUG_STATUS_0_INIT_SCONNECT_1_MASK (0x00000800U) #define CSL_GPU_DEBUG_STATUS_0_INIT_SCONNECT_1_SHIFT (11U) #define CSL_GPU_DEBUG_STATUS_0_INIT_SCONNECT_1_RESETVAL (0x00000000U) #define CSL_GPU_DEBUG_STATUS_0_INIT_SCONNECT_1_MAX (0x00000001U) #define CSL_GPU_DEBUG_STATUS_0_INIT_SCONNECT_0_MASK (0x00000400U) #define CSL_GPU_DEBUG_STATUS_0_INIT_SCONNECT_0_SHIFT (10U) #define CSL_GPU_DEBUG_STATUS_0_INIT_SCONNECT_0_RESETVAL (0x00000000U) #define CSL_GPU_DEBUG_STATUS_0_INIT_SCONNECT_0_MAX (0x00000001U) #define CSL_GPU_DEBUG_STATUS_0_INIT_MCONNECT_MASK (0x00000300U) #define CSL_GPU_DEBUG_STATUS_0_INIT_MCONNECT_SHIFT (8U) #define CSL_GPU_DEBUG_STATUS_0_INIT_MCONNECT_RESETVAL (0x00000000U) #define CSL_GPU_DEBUG_STATUS_0_INIT_MCONNECT_MAX (0x00000003U) #define CSL_GPU_DEBUG_STATUS_0_TARGET_SIDLEACK_MASK (0x000000C0U) #define CSL_GPU_DEBUG_STATUS_0_TARGET_SIDLEACK_SHIFT (6U) #define CSL_GPU_DEBUG_STATUS_0_TARGET_SIDLEACK_RESETVAL (0x00000000U) #define CSL_GPU_DEBUG_STATUS_0_TARGET_SIDLEACK_MAX (0x00000003U) #define CSL_GPU_DEBUG_STATUS_0_TARGET_SDISCACK_MASK (0x00000030U) #define CSL_GPU_DEBUG_STATUS_0_TARGET_SDISCACK_SHIFT (4U) #define CSL_GPU_DEBUG_STATUS_0_TARGET_SDISCACK_RESETVAL (0x00000000U) #define CSL_GPU_DEBUG_STATUS_0_TARGET_SDISCACK_MAX (0x00000003U) #define CSL_GPU_DEBUG_STATUS_0_TARGET_SIDLEREQ_MASK (0x00000008U) #define CSL_GPU_DEBUG_STATUS_0_TARGET_SIDLEREQ_SHIFT (3U) #define CSL_GPU_DEBUG_STATUS_0_TARGET_SIDLEREQ_RESETVAL (0x00000000U) #define CSL_GPU_DEBUG_STATUS_0_TARGET_SIDLEREQ_MAX (0x00000001U) #define CSL_GPU_DEBUG_STATUS_0_TARGET_SCONNECT_MASK (0x00000004U) #define CSL_GPU_DEBUG_STATUS_0_TARGET_SCONNECT_SHIFT (2U) #define CSL_GPU_DEBUG_STATUS_0_TARGET_SCONNECT_RESETVAL (0x00000000U) #define CSL_GPU_DEBUG_STATUS_0_TARGET_SCONNECT_MAX (0x00000001U) #define CSL_GPU_DEBUG_STATUS_0_TARGET_MCONNECT_MASK (0x00000003U) #define CSL_GPU_DEBUG_STATUS_0_TARGET_MCONNECT_SHIFT (0U) #define CSL_GPU_DEBUG_STATUS_0_TARGET_MCONNECT_RESETVAL (0x00000000U) #define CSL_GPU_DEBUG_STATUS_0_TARGET_MCONNECT_MAX (0x00000003U) #define CSL_GPU_DEBUG_STATUS_0_RESETVAL (0x00000000U) /* DEBUG_STATUS_1 */ #define CSL_GPU_DEBUG_STATUS_1_CMD_DEBUG_STATE_MASK (0x80000000U) #define CSL_GPU_DEBUG_STATUS_1_CMD_DEBUG_STATE_SHIFT (31U) #define CSL_GPU_DEBUG_STATUS_1_CMD_DEBUG_STATE_RESETVAL (0x00000000U) #define CSL_GPU_DEBUG_STATUS_1_CMD_DEBUG_STATE_MAX (0x00000001U) #define CSL_GPU_DEBUG_STATUS_1_CMD_RESP_DEBUG_STATE_MASK (0x40000000U) #define CSL_GPU_DEBUG_STATUS_1_CMD_RESP_DEBUG_STATE_SHIFT (30U) #define CSL_GPU_DEBUG_STATUS_1_CMD_RESP_DEBUG_STATE_RESETVAL (0x00000000U) #define CSL_GPU_DEBUG_STATUS_1_CMD_RESP_DEBUG_STATE_MAX (0x00000001U) #define CSL_GPU_DEBUG_STATUS_1_TARGET_IDLE_MASK (0x20000000U) #define CSL_GPU_DEBUG_STATUS_1_TARGET_IDLE_SHIFT (29U) #define CSL_GPU_DEBUG_STATUS_1_TARGET_IDLE_RESETVAL (0x00000000U) #define CSL_GPU_DEBUG_STATUS_1_TARGET_IDLE_MAX (0x00000001U) #define CSL_GPU_DEBUG_STATUS_1_RESP_FIFO_FULL_MASK (0x10000000U) #define CSL_GPU_DEBUG_STATUS_1_RESP_FIFO_FULL_SHIFT (28U) #define CSL_GPU_DEBUG_STATUS_1_RESP_FIFO_FULL_RESETVAL (0x00000000U) #define CSL_GPU_DEBUG_STATUS_1_RESP_FIFO_FULL_MAX (0x00000001U) #define CSL_GPU_DEBUG_STATUS_1_CMD_FIFO_FULL_MASK (0x08000000U) #define CSL_GPU_DEBUG_STATUS_1_CMD_FIFO_FULL_SHIFT (27U) #define CSL_GPU_DEBUG_STATUS_1_CMD_FIFO_FULL_RESETVAL (0x00000000U) #define CSL_GPU_DEBUG_STATUS_1_CMD_FIFO_FULL_MAX (0x00000001U) #define CSL_GPU_DEBUG_STATUS_1_RESP_ERROR_MASK (0x04000000U) #define CSL_GPU_DEBUG_STATUS_1_RESP_ERROR_SHIFT (26U) #define CSL_GPU_DEBUG_STATUS_1_RESP_ERROR_RESETVAL (0x00000000U) #define CSL_GPU_DEBUG_STATUS_1_RESP_ERROR_MAX (0x00000001U) #define CSL_GPU_DEBUG_STATUS_1_WHICH_TARGET_REGISTER_MASK (0x03E00000U) #define CSL_GPU_DEBUG_STATUS_1_WHICH_TARGET_REGISTER_SHIFT (21U) #define CSL_GPU_DEBUG_STATUS_1_WHICH_TARGET_REGISTER_RESETVAL (0x00000000U) #define CSL_GPU_DEBUG_STATUS_1_WHICH_TARGET_REGISTER_MAX (0x0000001fU) #define CSL_GPU_DEBUG_STATUS_1_TARGET_CMD_OUT_MASK (0x001C0000U) #define CSL_GPU_DEBUG_STATUS_1_TARGET_CMD_OUT_SHIFT (18U) #define CSL_GPU_DEBUG_STATUS_1_TARGET_CMD_OUT_RESETVAL (0x00000000U) #define CSL_GPU_DEBUG_STATUS_1_TARGET_CMD_OUT_MAX (0x00000007U) #define CSL_GPU_DEBUG_STATUS_1_INIT_MSTANDBY_MASK (0x00020000U) #define CSL_GPU_DEBUG_STATUS_1_INIT_MSTANDBY_SHIFT (17U) #define CSL_GPU_DEBUG_STATUS_1_INIT_MSTANDBY_RESETVAL (0x00000000U) #define CSL_GPU_DEBUG_STATUS_1_INIT_MSTANDBY_MAX (0x00000001U) #define CSL_GPU_DEBUG_STATUS_1_INIT_MWAIT_MASK (0x00010000U) #define CSL_GPU_DEBUG_STATUS_1_INIT_MWAIT_SHIFT (16U) #define CSL_GPU_DEBUG_STATUS_1_INIT_MWAIT_RESETVAL (0x00000000U) #define CSL_GPU_DEBUG_STATUS_1_INIT_MWAIT_MAX (0x00000001U) #define CSL_GPU_DEBUG_STATUS_1_INIT_MDISCREQ_MASK (0x00008000U) #define CSL_GPU_DEBUG_STATUS_1_INIT_MDISCREQ_SHIFT (15U) #define CSL_GPU_DEBUG_STATUS_1_INIT_MDISCREQ_RESETVAL (0x00000000U) #define CSL_GPU_DEBUG_STATUS_1_INIT_MDISCREQ_MAX (0x00000001U) #define CSL_GPU_DEBUG_STATUS_1_INIT_MDISCACK_MASK (0x00006000U) #define CSL_GPU_DEBUG_STATUS_1_INIT_MDISCACK_SHIFT (13U) #define CSL_GPU_DEBUG_STATUS_1_INIT_MDISCACK_RESETVAL (0x00000000U) #define CSL_GPU_DEBUG_STATUS_1_INIT_MDISCACK_MAX (0x00000003U) #define CSL_GPU_DEBUG_STATUS_1_INIT_SCONNECT_2_MASK (0x00001000U) #define CSL_GPU_DEBUG_STATUS_1_INIT_SCONNECT_2_SHIFT (12U) #define CSL_GPU_DEBUG_STATUS_1_INIT_SCONNECT_2_RESETVAL (0x00000000U) #define CSL_GPU_DEBUG_STATUS_1_INIT_SCONNECT_2_MAX (0x00000001U) #define CSL_GPU_DEBUG_STATUS_1_INIT_SCONNECT_1_MASK (0x00000800U) #define CSL_GPU_DEBUG_STATUS_1_INIT_SCONNECT_1_SHIFT (11U) #define CSL_GPU_DEBUG_STATUS_1_INIT_SCONNECT_1_RESETVAL (0x00000000U) #define CSL_GPU_DEBUG_STATUS_1_INIT_SCONNECT_1_MAX (0x00000001U) #define CSL_GPU_DEBUG_STATUS_1_INIT_SCONNECT_0_MASK (0x00000400U) #define CSL_GPU_DEBUG_STATUS_1_INIT_SCONNECT_0_SHIFT (10U) #define CSL_GPU_DEBUG_STATUS_1_INIT_SCONNECT_0_RESETVAL (0x00000000U) #define CSL_GPU_DEBUG_STATUS_1_INIT_SCONNECT_0_MAX (0x00000001U) #define CSL_GPU_DEBUG_STATUS_1_INIT_MCONNECT_MASK (0x00000300U) #define CSL_GPU_DEBUG_STATUS_1_INIT_MCONNECT_SHIFT (8U) #define CSL_GPU_DEBUG_STATUS_1_INIT_MCONNECT_RESETVAL (0x00000000U) #define CSL_GPU_DEBUG_STATUS_1_INIT_MCONNECT_MAX (0x00000003U) #define CSL_GPU_DEBUG_STATUS_1_TARGET_SIDLEACK_MASK (0x000000C0U) #define CSL_GPU_DEBUG_STATUS_1_TARGET_SIDLEACK_SHIFT (6U) #define CSL_GPU_DEBUG_STATUS_1_TARGET_SIDLEACK_RESETVAL (0x00000000U) #define CSL_GPU_DEBUG_STATUS_1_TARGET_SIDLEACK_MAX (0x00000003U) #define CSL_GPU_DEBUG_STATUS_1_TARGET_SDISCACK_MASK (0x00000030U) #define CSL_GPU_DEBUG_STATUS_1_TARGET_SDISCACK_SHIFT (4U) #define CSL_GPU_DEBUG_STATUS_1_TARGET_SDISCACK_RESETVAL (0x00000000U) #define CSL_GPU_DEBUG_STATUS_1_TARGET_SDISCACK_MAX (0x00000003U) #define CSL_GPU_DEBUG_STATUS_1_TARGET_SIDLEREQ_MASK (0x00000008U) #define CSL_GPU_DEBUG_STATUS_1_TARGET_SIDLEREQ_SHIFT (3U) #define CSL_GPU_DEBUG_STATUS_1_TARGET_SIDLEREQ_RESETVAL (0x00000000U) #define CSL_GPU_DEBUG_STATUS_1_TARGET_SIDLEREQ_MAX (0x00000001U) #define CSL_GPU_DEBUG_STATUS_1_TARGET_SCONNECT_MASK (0x00000004U) #define CSL_GPU_DEBUG_STATUS_1_TARGET_SCONNECT_SHIFT (2U) #define CSL_GPU_DEBUG_STATUS_1_TARGET_SCONNECT_RESETVAL (0x00000000U) #define CSL_GPU_DEBUG_STATUS_1_TARGET_SCONNECT_MAX (0x00000001U) #define CSL_GPU_DEBUG_STATUS_1_TARGET_MCONNECT_MASK (0x00000003U) #define CSL_GPU_DEBUG_STATUS_1_TARGET_MCONNECT_SHIFT (0U) #define CSL_GPU_DEBUG_STATUS_1_TARGET_MCONNECT_RESETVAL (0x00000000U) #define CSL_GPU_DEBUG_STATUS_1_TARGET_MCONNECT_MAX (0x00000003U) #define CSL_GPU_DEBUG_STATUS_1_RESETVAL (0x00000000U) #ifdef __cplusplus } #endif #endif