TI Keystone PCIe interface

Keystone PCI host Controller is based on Designware PCI h/w version 3.65.
It shares common functions with PCIe Designware core driver and inherit
common properties defined in
Documentation/devicetree/bindings/pci/designware-pci.txt

Please refer to Documentation/devicetree/bindings/pci/designware-pci.txt
for the details of Designware DT bindings.  Additional properties are
described here as well as properties that are not applicable.

Required Properties:-

compatibility: Should be "ti,keystone-pcie" for RC
	       Should be "ti,keystone-pcie-ep" for EP

Optional properties:-
	phys: phandle to Generic Keystone SerDes phy for PCI
	phy-names: name of the Generic Keystine SerDes phy for PCI
	  - If boot loader already does PCI link establishment, then phys and
	    phy-names shouldn't be present.
	interrupts: platform interrupt for error interrupts.
	ti,syscon-dev: phandle to the syscon dt node. The 1st argument should
		       contain the register offset within syscon dt node to set
		       the PCIe mode.

Designware DT Properties not applicable for Keystone PCI

1. pcie_bus clock-names not used.  Instead, a phandle to phys is used.

HOST MODE
=========
reg:	index 1 is the base address and length of DW application registers.
	index 2 is the base address and length of PCI device ID register.

pcie_msi_intc : Interrupt controller device node for MSI IRQ chip
	interrupt-cells: should be set to 1
	interrupt-parent: Parent interrupt controller phandle
	interrupts: GIC interrupt lines connected to PCI MSI interrupt lines

 Example:
	pcie_msi_intc: msi-interrupt-controller {
			interrupt-controller;
			#interrupt-cells = <1>;
			interrupt-parent = <&gic>;
			interrupts = <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 31 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 32 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 33 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 37 IRQ_TYPE_EDGE_RISING>;
	};

pcie_intc: Interrupt controller device node for Legacy IRQ chip
	interrupt-cells: should be set to 1
	interrupt-parent: Parent interrupt controller phandle
	interrupts: GIC interrupt lines connected to PCI Legacy interrupt lines

 Example:
	pcie_intc: legacy-interrupt-controller {
		interrupt-controller;
		#interrupt-cells = <1>;
		interrupt-parent = <&gic>;
		interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 27 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 28 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 29 IRQ_TYPE_EDGE_RISING>;
	};

DEVICE MODE
===========
reg: Three register ranges as listed in the reg-names property
reg-names: "ep_dbics" for the standard configuration registers as they
	    are locally accessed within the DIF CS/CS2 space
	   "app" for the PCIe SS application registers
	   "addr_space" used to map remote RC address space
num-ib-windows : number of inbound address translation windows